Static Storage TRIZ Cases
- LDO In-Rush Control Circuit for Power-Up Voltage Slope Matching
Shorting external and internal voltages during power-up equalizes rise slopes, suppressing in-rush current and protecting peripheral circuits.
- 3D DRAM Cell Layout With Horizontally Offset Capacitor-Transistor Pairs
Vertically stacked DRAM cells place capacitors horizontally offset from transistors to raise integration density while managing layout complexity.
- Phase Change Memory Interconnect Layout for Lower Parasitic Capacitance
A third insulating layer with full-height vias improves phase change memory connectivity while reducing parasitic capacitance in chip integration.
- Planar Transistor-Capacitor Memory Cell Layout for Higher Integration
A horizontally offset transistor-capacitor layout reduces multi-layer alignment burden while supporting denser, better-performing memory arrays.
- Phase Change Memory Cell Structure for Low-Capacitance Integration
Trench-separated substrate regions and stacked vias integrate phase change memory cells with lower parasitic capacitance and smaller footprints.