Semiconductor Device Syndrome Signal Comparison for Latent Failure Detection
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Solution Overview
Problem
Existing semiconductor devices lack effective mechanisms to detect latent failures in data storage, particularly in synchronous semiconductor devices like DDR and SDR, which can lead to undetected errors and defective memory cells.
Innovation Solution
A semiconductor device incorporating a syndrome generation circuit and a failure detection circuit that generates and compares syndrome signals across multiple pulses of a test signal to identify inconsistencies, enabling a failure detection signal if logic level combinations differ, thus detecting latent failures and potential defective memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a syndrome generation circuit and failure detection circuit are added to detect latent failures, then reliability is improved, but device complexity increases
Solution Approach 1:
The failure detection function is segmented into distinct circuit modules: a syndrome generation circuit that generates syndrome signals from data signals, and a failure detection circuit that stores and compares syndrome signals across multiple clock cycles. This segmentation allows each module to perform a specific function, improving reliability while making the overall complexity manageable through functional decomposition.
Solution Approach 2:
The patent introduces syndrome signals as an intermediary element between the data storage circuit and the failure detection mechanism. The syndrome generation circuit produces syndrome signals that encode error information, and the failure detection circuit uses these intermediate signals to detect failures without directly analyzing the original data signals, thus enabling reliable detection while maintaining circuit modularity.
2Measurement precision
If syndrome signals are stored and compared across multiple pulses to detect errors, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The failure detection circuit operates by periodically storing syndrome signals at different clock cycles (first pulse, second pulse, etc.) and comparing them in a periodic manner. This periodic action allows the system to accumulate error detection information over multiple cycles, improving measurement precision for detecting latent failures while maintaining a regular, predictable timing pattern that minimizes time loss.
Solution Approach 2:
The syndrome signals are generated and stored in advance during normal operation before failures manifest. The failure detection circuit preliminarily stores syndrome signals from multiple clock cycles, so when a comparison is needed, the data is already prepared and available, reducing the time required for actual failure detection and analysis.
Data Source
AI summary
A semiconductor device may include a syndrome generation circuit and a failure detection circuit. The syndrome generation circuit may generate a syndrome signal corresponding to a pattern of an output data signal. The failure detection circuit may detect the syndrome signal and sequentially store the syndrome signal to generate a first syndrome signal and a second syndrome signal if an error is detected from the syndrome signal. The failure detection circuit may generate a failure detection signal which is enabled if a logic level combination of the first syndrome signal is different from a logic level combination of the second syndrome signal.