3D Stacked Memory Layout for Low-Power AR Image Capture
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Solution Overview
Problem
Existing artificial reality devices face challenges in reducing power consumption and chip size while maintaining high-resolution image capture and long duration operation, particularly in wearable devices.
Innovation Solution
Implementing a 3D stacked memory architecture with a customized memory page configuration, low power DRAM die, and Network-on-Chip (NoC) architecture, eliminating the need for physical interface circuitry and impedance matching, and using unidirectional/bidirectional links for data transfer between memory banks and System-on-Chip (SoC).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If conventional 2D memory architecture is used, then chip area is larger and power consumption is higher, but manufacturing complexity is lower
Solution Approach 1:
The patent transitions from conventional 2D memory architecture to 3D stacked memory architecture, stacking multiple memory dies vertically to increase storage capacity and improve power efficiency without proportionally increasing chip area. This dimensional change enables better thermal management and reduced power consumption while maintaining manufacturing feasibility through established 3D packaging techniques.
Solution Approach 2:
The patent integrates multiple memory banks and controllers into a unified 3D stacked structure, combining multiple memory dies with interconnect layers to create a compact high-capacity memory system. This merging approach reduces overall system power consumption by optimizing data access paths and reducing transmission distances within the stacked architecture.
2Quantity of substance
If 3D stacked memory is implemented, then power consumption is reduced and chip density increases, but manufacturing complexity increases
Solution Approach 1:
The patent employs 3D stacking to vertically arrange multiple memory dies, significantly increasing chip density and storage capacity within a smaller footprint. This dimensional transition enables higher quantities of memory cells per unit area while managing manufacturing complexity through standardized 3D integration processes.
Solution Approach 2:
The patent divides the memory system into multiple separate dies that are stacked vertically, with each die containing specific memory banks or controllers. This segmentation allows independent optimization of each die layer and simplifies the manufacturing process by enabling separate fabrication and testing of individual dies before final assembly.
3Productivity
If parallel memory bank access is implemented, then data transmission efficiency improves, but device complexity increases
Solution Approach 1:
The patent divides the memory system into multiple independently accessible memory banks arranged in a parallel architecture. Each memory bank can be accessed simultaneously through dedicated interconnect paths, significantly improving data transmission efficiency and throughput while managing complexity through modular design principles.
Solution Approach 2:
The patent implements a universal memory controller architecture that can manage multiple memory banks through standardized interfaces and protocols. This multi-functional controller design enables efficient parallel access to different memory banks while maintaining system coherence and reducing overall device complexity through interface standardization.
Data Source
AI summary
A stacked three-dimensional (3D) memory architecture is provided. An example stacked 3D memory architecture is included in a system and/or device, such as augmented reality glasses. Example augmented reality glasses include a camera, a 3D stacked memory, and a System-on-Chip (SoC). The 3D stacked memory is communicatively coupled with the camera and is configured to store image data captured by the camera. The 3D stacked memory includes a plurality of memory banks. The SoC is coupled with the 3D stacked memory. Additionally, the SoC is vertically stacked with the 3D stacked memory via a plurality of die-to-die interconnections between the SoC and the plurality of memory banks, includes a memory controller for accessing one or more memory banks of the plurality of memory banks, and is configured to process the image data stored in the 3D stacked memory.