Flash Memory Cell Layout With Alternating Branch Doped Isolation
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Solution Overview
Problem
As semiconductor devices, particularly memory devices, scale down, the reduced spacing between adjacent floating gates in flash memory leads to issues such as shorting and improper isolation due to process variations, which conventional shallow trench isolations cannot adequately address.
Innovation Solution
A novel flash memory structure is introduced, featuring branch doped regions alternately arranged at both sides of the source line, isolated by shallow trench isolations. This design enhances process window and reduces layout area while preventing shorting between adjacent floating gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dimension of semiconductor device is scaled down to provide more memory capacity, then the memory capacity increases, but the spacing between adjacent floating gates becomes smaller leading to shorting and improper isolation
Solution Approach 1:
The patent divides the isolation structure into multiple segments: shallow trench isolations (STIs) for basic device isolation, and additional branch doped regions alternately arranged at two sides of the source line for enhanced isolation. This segmented approach provides multi-level isolation that prevents shorting between adjacent floating gates while maintaining scaled dimensions for high memory capacity.
Solution Approach 2:
The patent applies different doping characteristics to different regions: the branch doped regions are alternately arranged at two sides of the source line with specific doping types and concentrations tailored to local isolation needs. This local quality enhancement ensures proper isolation effect in critical areas where floating gates are closely spaced, while maintaining overall device performance.
2Device complexity
If conventional shallow trench isolations are used for device isolation, then the structure is simple, but the isolation effect is insufficient due to process variation
Solution Approach 1:
The patent incorporates branch doped regions alternately arranged at two sides of the source line as a preliminary isolation measure before final device formation. This preliminary action creates an isolation barrier that compensates for potential process variations, ensuring that even if STI dimensions vary, the alternating doped regions maintain proper isolation between adjacent floating gates.
3Area of stationary object
If the spacing between adjacent floating gates is reduced to increase memory capacity, then more memory cells fit in limited area, but process window is reduced making isolation difficult
Solution Approach 1:
The patent employs asymmetric arrangement of branch doped regions alternately positioned at two sides of the source line rather than symmetric placement. This asymmetric configuration optimizes the process window by creating isolation barriers that are more tolerant to dimensional variations, enabling reliable isolation even when floating gate spacing is minimized to increase memory cell density in limited layout area.
Data Source
AI summary
A flash memory structure is provided in the present invention, including an active area and STIs, wherein the diffusion doped region includes a source line doped region extending in a first direction and multiple branch doped regions extending in a second direction at two sides of the source line doped region and alternately arranged along the first direction, and these branch doped regions are isolated by the STIs. An erase gate are on the source line doped region and extends in the first direction, multiple floating gates are on the branch doped regions at two sides of the erase gate, and two word lines respectively at outer sides of the floating gates and extend through multiple branch doped regions in the first direction.