FVF LDO Regulator with Common-Gate Boost for Supply Noise Attenuation
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Solution Overview
Problem
Existing LDO regulator circuits struggle to effectively attenuate supply voltage noise across all frequency bands, particularly when load current is high, and their transient response is limited by bandwidth constraints.
Innovation Solution
An LDO regulator circuit apparatus utilizing a flip voltage follower (FVF) rectifier circuit, error amplifying circuit, common gate circuit, and super source follower circuit, along with a class-AB structure to control the gate node of the pass transistor, enabling noise attenuation across all frequency bands and improved transient response in both overshoot and undershoot conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a conventional LDO regulator circuit is used, then the circuit structure is simple, but the supply voltage noise cannot be attenuated in all frequency bands especially at high frequencies
Solution Approach 1:
The LDO regulator circuit is segmented into multiple functional blocks: error amplifying circuit, common gate circuit, super source follower circuit, and FVF rectifier circuit. Each block handles specific frequency ranges and functions, allowing comprehensive noise attenuation across all frequency bands while maintaining manageable circuit complexity through modular design.
Solution Approach 2:
The patent combines multiple circuit techniques (error amplification, common gate configuration, super source follower, and FVF rectification) into a single integrated LDO regulator circuit. This merging of functions enables the circuit to achieve broad-spectrum noise attenuation that would be difficult to accomplish with any single technique alone.
2Object-affected harmful factors
If the LDO loop bandwidth is increased to improve noise attenuation, then the noise reduction capability improves, but the transient response speed becomes slower
Solution Approach 1:
The LDO regulator circuit employs dynamic compensation techniques through the error amplifying circuit and super source follower circuit, which adjust their operation based on real-time conditions. This dynamic behavior allows the circuit to maintain both wide bandwidth for noise attenuation and fast transient response, resolving the traditional trade-off between these two parameters.
Solution Approach 2:
The patent utilizes parameter changes in the error amplifying circuit and common gate circuit to optimize both noise attenuation and transient response. By carefully selecting and adjusting circuit parameters (such as transistor dimensions, bias currents, and feedback ratios), the circuit achieves improved PSR across all frequency bands while maintaining fast transient response characteristics.
3Power
If the load current is increased to meet high current demands, then the power delivery capability improves, but the supply voltage noise attenuation deteriorates
Solution Approach 1:
The error amplifying circuit provides strong negative feedback that becomes even more effective at high load currents. The feedback mechanism continuously monitors the output voltage and adjusts the pass transistor gate voltage to compensate for noise, maintaining excellent noise attenuation performance regardless of load current magnitude.
Solution Approach 2:
The FVF rectifier circuit automatically compensates for voltage drops and noise at the output node based on the actual load conditions. This self-service mechanism ensures that noise attenuation performance is maintained dynamically adapting to varying load currents without external intervention.
Data Source
AI summary
An LDO regulator circuit apparatus capable of attenuating supply voltage noise is disclosed. The LDO regulator circuit apparatus capable of attenuating supply voltage noise comprises a flip voltage follower (FVF) rectifier circuit unit having a pass transistor MPASS configured to adjust a supply voltage to output an output voltage; an error amplifying circuit unit configured to receive and compare a reference signal (VREF) and a feedback voltage (VOUT_DIV), wherein the feedback voltage is fed back through the output voltage through a feedback loop; a common gate (CG) circuit unit configured to amplify a feedback loop gain of the flip voltage follower (FVF) rectifier circuit unit; and a super source follower circuit unit configured to buffer an output of the CG circuit unit and transmit it to a gate node of the pass transistor (MPASS).