3D Memory Cell Access Line Layout With Sacrificial Via Routing
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in interconnect structure design, particularly in accessing and operating memory device cells, leading to increased complexity and reduced scalability due to high aspect ratio etching and potential damage to storage layers during via formation.
Innovation Solution
The method involves forming a sacrificial via in a dielectric layer over a substrate, creating a stack of layers for the memory cell array, forming a trench corresponding to the sacrificial via, removing the via to form a via hole, and filling both the trench and via hole with a conductive material, which improves the overlay window and avoids high aspect ratio etching, thereby enhancing production yield and memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional interconnect structures are used to access memory device cells, then device integration is achieved, but memory cell density and scalability are limited
Solution Approach 1:
The patent transitions from planar interconnect structures to three-dimensional vertical gate lines that extend through multiple layers. This dimensional change allows interconnects to access memory cells in the vertical direction, significantly increasing memory cell density without proportionally increasing interconnect structure complexity.
Solution Approach 2:
The vertical gate lines are formed by nesting multiple material layers (conductive layers, dielectric layers, and sacrificial layers) within each other. The sacrificial layers are deposited and patterned, then removed to create voids that are subsequently filled with conductive material, creating a nested construction approach that achieves complex 3D interconnects through sequential layer deposition.
2Productivity
If memory device cell design is reduced to increase capacity, then integration increases, but interconnect structure design becomes more challenging
Solution Approach 1:
The interconnect structure is segmented into distinct functional layers: sacrificial layers for pattern definition, dielectric layers for insulation and structural support, and conductive layers for electrical connectivity. This segmentation allows each layer to be optimized and fabricated independently, simplifying the overall design process despite increased integration requirements.
Solution Approach 2:
Sacrificial layers are deposited and patterned in advance before the final conductive structures are formed. These preliminary sacrificial structures guide the subsequent formation of vertical gate lines and define the interconnect geometry, making the complex 3D interconnect design more manageable through pre-planned pattern transfer.
3Quantity of substance
If vertical gate lines are formed through multiple layers, then memory cell density increases, but risk of damage to storage layers increases
Solution Approach 1:
Dielectric layers are deposited beforehand to provide cushioning and protection during the formation of vertical gate lines. These dielectric layers act as protective barriers that prevent damage to underlying storage layers when conductive materials are deposited and patterned, ensuring storage layer integrity while enabling high-density vertical interconnects.
Solution Approach 2:
Sacrificial layers serve as intermediary structures that facilitate the formation of vertical gate lines without directly contacting or damaging storage layers. These temporary structures are deposited, patterned, and then removed, leaving clean voids for conductive material deposition while protecting storage layers from direct exposure to potentially damaging fabrication processes.
Data Source
AI summary
A semiconductor memory device is provided. The semiconductor memory device includes a first access line extending in a horizontal direction, a first column of memory cells over the first access line, a second column of memory cells adjacent to the first column of memory cells, and a second access line over the first column of memory cells and the second column of memory cells and extending in the horizontal direction. The first column of memory cells includes a first gate line electrically connected to the first access line, and the second column of memory cells includes a second gate line electrically connected to the second access line.