Underground Silicon Interconnect Layout for Compact Transistor Contacts
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Solution Overview
Problem
Current integrated circuits face challenges in reducing area, power consumption, and noise due to large source or drain diffusion areas required for connecting metal wires, which increase capacitance and complexity, especially as device dimensions shrink to meet scaling demands.
Innovation Solution
A semiconductor device structure with underground interconnections embedded in a silicon substrate, utilizing self-aligned contact technology to connect transistors vertically to source or drain, reducing the need for surface area and optimizing isolation, allowing for more efficient signal transmission and reduced complexity above the silicon surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional metal wire interconnections with contact holes are used to connect transistors, then signal transmission between gate, source, and drain is achieved, but the source or drain diffusion area must be enlarged to accommodate contact holes, which increases area consumption, capacitance, power consumption, and noise
Solution Approach 1:
The patent moves the interconnection from the traditional planar surface (2D) to an underground embedded structure (3D), placing metal interconnection layers below the silicon substrate surface. This dimensional transition allows contact holes to access conductive regions from the bottom rather than requiring large surface diffusion areas, thereby reducing area consumption while maintaining reliable signal transmission.
Solution Approach 2:
Instead of connecting to the top surface of conductive regions through contact holes as in traditional designs, the patent inverts the connection approach by accessing conductive regions from beneath the substrate. The interconnection structure approaches the conductive regions from the opposite direction (bottom-up rather than top-down), eliminating the need for large surface diffusion areas.
2Manufacturing precision
If source or drain diffusion areas are enlarged to ensure proper contact hole alignment, then lithographic misalignment tolerance is improved, but transistor diffusion areas increase, leading to larger die area and increased capacitance
Solution Approach 1:
By transitioning to underground embedded interconnections, the patent accesses conductive regions vertically from beneath the substrate rather than laterally from the surface. This eliminates the need for large diffusion areas that were previously required to provide alignment tolerance for contact holes, as the vertical access path from below does not suffer from the same lithographic alignment constraints.
3Device complexity
If more interconnection layers are added above the silicon surface to reduce complexity, then signal routing becomes easier, but contact areas increase and area penalty is incurred
Solution Approach 1:
The patent introduces underground interconnection layers below the substrate surface, creating additional routing dimensions without increasing the planar footprint. This allows complex signal routing to be achieved in the vertical dimension beneath the surface, eliminating the need to add more lateral interconnection layers that would increase contact areas and area penalty.
Data Source
AI summary
A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.