Subsurface Interconnect Layout for Compact Semiconductor Transistors
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Solution Overview
Problem
Current integrated circuits face challenges in reducing area, power consumption, and noise due to large source or drain diffusion areas required for connecting metal wires, which increases capacitance and complexity, especially as device dimensions shrink.
Innovation Solution
A semiconductor device structure with underground interconnections embedded in a silicon substrate, allowing for compact self-aligned connections to source or drain, reducing the need for surface area and optimizing isolation, thereby enhancing transistor and circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If metal wires with contact holes and connection plugs are used to connect transistors, then electrical connectivity is achieved, but the source or drain diffusion area must be enlarged to accommodate photolithographic misalignment, resulting in increased area consumption and capacitance
Solution Approach 1:
The patent moves the interconnection from the surface plane to the subsurface dimension by embedding metal wires below the silicon surface. This dimensional transition eliminates the need for surface contact holes and allows direct vertical connection to source/drain regions, thereby reducing the required diffusion area while maintaining electrical connectivity.
Solution Approach 2:
Instead of connecting transistors from the surface downward through contact holes, the patent inverts the approach by placing interconnections below the surface and connecting upward to source/drain regions. This inverted architecture eliminates photolithographic alignment constraints and reduces the diffusion area required for connections.
2Reliability
If larger source or drain diffusion areas are designed to accommodate contact holes, then connectivity is maintained, but the die area increases and capacitance increases causing AC performance penalties
Solution Approach 1:
By transitioning the interconnection architecture from surface-level to subsurface embedding, the patent reduces the footprint required for connections. This dimensional change allows smaller source/drain diffusion areas while maintaining reliable connectivity, thereby improving AC performance by reducing parasitic capacitance.
3Adaptability or versatility
If multiple interconnection layers are used above the silicon surface to transfer signals, then signal routing flexibility is achieved, but the device complexity and number of components increase
Solution Approach 1:
The patent utilizes the subsurface dimension for signal routing, embedding metal wires at different depths below the silicon surface. This vertical stacking in the subsurface region provides signal routing flexibility equivalent to multiple surface layers, while reducing overall device complexity by consolidating interconnection functions in the third dimension.
Solution Approach 2:
The patent implements a nested interconnection architecture where metal wires are embedded at different subsurface levels, with each layer nested within the substrate volume. This nested structure provides multiple routing paths and signal distribution capabilities while maintaining a compact overall device structure.
Data Source
AI summary
A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.