Failure Bit Detection Circuit Using Shared Current Mirror
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Solution Overview
Problem
Conventional memory devices face increased power consumption and reduced response rates due to the large number of pull-down current sources required for failure bits detection, especially as the number of memory cells grows, which compromises detection accuracy.
Innovation Solution
A failure bits detector comprising a current generator, current mirror, and comparator that generates a first current and mirrors it to produce a second current, limiting power consumption by decoupling the second current from the failure bit count, thereby enhancing detection efficiency and reducing power waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to increase memory density, then the memory capacity is improved, but the number of possible failure bits increases significantly, leading to increased power consumption in the detection mechanism
Solution Approach 1:
The patent merges multiple pull-down current sources into a single shared current source that serves all memory cells. Instead of having separate current sources for each failure bit detection, one current source is shared across the entire memory array, dramatically reducing the number of current sources from potentially thousands to just one, thereby reducing power consumption proportionally.
Solution Approach 2:
The shared pull-down current source performs multiple functions simultaneously - it can detect failure bits across the entire memory array regardless of which specific cell fails. The current source is not dedicated to a single cell or small group of cells but serves as a universal detection resource for all memory cells, increasing resource utilization efficiency.
2Reliability
If the number of pull-down current sources is increased to detect more failure bits, then the detection coverage is improved, but the load on the detection mechanism increases and reduces the response rate
Solution Approach 1:
Multiple detection functions are merged into a single current source and shared resource. The shared current source can detect failure bits across the entire memory array, providing full detection coverage without requiring multiple separate current sources. This merging eliminates the load multiplication effect while maintaining comprehensive detection capability.
3Speed
If the sizes of related elements are increased to increase the response rate, then the detection speed is improved, but the accuracy of the detection operation is lowered
Solution Approach 1:
The patent introduces a page buffer as an intermediary element between the shared current source and the memory cells. The page buffer acts as a buffer that isolates the current source from direct loading effects, allowing the use of larger element sizes for improved response rate without sacrificing detection accuracy. The buffer absorbs the load variations and maintains signal integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces power consumption and accelerates the response rate of failure bits detection without compromising accuracy, improving the overall efficiency of the detection process.
Implementation Method 1
The current mirror has a first end coupled to the current generator. The current mirror has a second end coupled to a page buffer. The current mirror mirrors the first current to generate a second current at the second end of the current mirror.
Data Source
AI summary
A memory device, a failure bits detector, and a failure bits detection method thereof are provided. The failure bits detector includes a current generator, a current mirror, and a comparator. The current generator generates a first current according to a reference code. The current mirror mirrors the first current to generate a second current at a second end of the current mirror. The comparator compares a first voltage at a first input end with a second voltage at a second input end to generate a detection result.