3D Semiconductor Memory Contact Layout for Lower Resistance
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Solution Overview
Problem
The integration density of conventional two-dimensional semiconductor devices is limited by the need for expensive fine patterning technologies, and three-dimensional semiconductor memory devices are proposed to overcome this limitation.
Innovation Solution
A semiconductor memory device design featuring stacked wordlines, channel regions, source/drain regions, bitlines, data storage elements, and capping films with insertion holes and protruding portions to enhance contact area and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional two-dimensional semiconductor devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from conventional two-dimensional planar structures to three-dimensional stacked structures by vertically stacking multiple wordlines and channel regions. This dimensional change allows memory cells to be arranged in three dimensions rather than just on a plane, significantly increasing integration density without requiring proportionally more complex manufacturing processes
Solution Approach 2:
The patent implements nested structures where channel regions are surrounded by wordlines on multiple sides (gate-all-around structure), and data storage elements are positioned within the three-dimensional memory cell structure. This nesting approach maximizes space utilization and increases the number of memory cells that can be packed into a given volume
2Reliability
If contact area between semiconductor patterns and data storage elements is increased, then contact resistance decreases, but device structure becomes more complex
Solution Approach 1:
The patent utilizes the third dimension (vertical direction) to increase contact area. Capping films extend vertically with protruding portions that contact semiconductor patterns from above, and insertion holes provide vertical pathways for electrical connection. This vertical contact approach increases contact area without requiring larger lateral contact pads, thereby reducing contact resistance while maintaining a compact footprint
Solution Approach 2:
The patent introduces capping films as intermediary structures between the semiconductor patterns and data storage elements. These capping films include protruding portions that contact the semiconductor patterns and extend into insertion holes to contact the data storage elements, serving as a mediating contact structure that reduces overall contact resistance while distributing the contact interface across multiple locations
Data Source
AI summary
A semiconductor memory device semiconductor memory device includes a substrate, a plurality of wordlines stacked in a first direction on the substrate, channel regions between adjacent wordlines in the first direction and extending in a second direction, first source/drain regions on first sides of the channel regions, second source/drain regions on second sides of the channel regions, bitlines extending in the first direction on the substrate and connected to corresponding ones of the first source/drain regions, respectively, data storage elements connected to the second source/drain regions, respectively, and capping films between the second source/drain regions and corresponding ones of the data storage elements, respectively, the capping filing including insertion holes, respectively, wherein at least portions of the second source/drain regions are inserted into corresponding ones of the insertion holes of the capping films, respectively.