Planar Transistor-Capacitor Memory Cell Layout for Higher Integration
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Solution Overview
Problem
There is a need to improve the architectural layouts of integrated circuit structures to maintain device performance while achieving higher levels of integration, particularly in memory devices like DRAM, by developing improved devices and fabrication methods that integrate transistors and capacitors effectively.
Innovation Solution
The integration of transistors and capacitors at a common horizontal level within memory cells, with capacitors being horizontally offset from transistors and vertically stacked, allowing for the formation of vertically-stacked tiers of memory cells with tailored performance characteristics through variations in semiconductor materials and dopant concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional transistor designs with vertically stacked capacitors are used, then device density is improved, but manufacturing complexity and defect rates increase due to multi-layer alignment requirements
Solution Approach 1:
The patent transitions from vertical stacking (three-dimensional arrangement) to horizontal placement (two-dimensional arrangement) of capacitors relative to transistors. This dimensional change eliminates the need for complex multi-layer alignment while maintaining high device density through lateral packing optimization.
2Quantity of substance
If conventional multi-layer capacitor stacking is employed, then capacitance density is improved, but yield decreases due to alignment defects across multiple layers
Solution Approach 1:
The patent extracts the capacitor from the vertical stacking arrangement and places it horizontally adjacent to the transistor gate. This separation eliminates the alignment dependencies between vertical layers, thereby improving manufacturing yield while maintaining capacitance density through optimized horizontal spacing.
3Area of stationary object
If vertically stacked capacitor-transistor structures are used, then area efficiency is improved, but process variability and defect sensitivity increase
Solution Approach 1:
The patent repositions capacitors from vertical stacking to horizontal placement alongside transistor gates. This dimensional transition reduces sensitivity to alignment precision requirements while maintaining area efficiency through optimized lateral spacing and gate bracketing configurations.
4Adaptability or versatility
If complex multi-layer alignment processes are used for vertically stacked devices, then device integration is improved, but manufacturing cost and time increase
Solution Approach 1:
The patent extracts capacitors from multi-layer vertical stacking and places them horizontally adjacent to transistor gates within the same planar level. This eliminates complex multi-layer alignment processes, reducing manufacturing cycle time while maintaining device integration through lateral coupling structures.
Data Source
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AI summary
An assembly comprising: a first insulative level over a semiconductor base; a second insulative level over the first insulative level; and a device between the first and second insulative levels; the device including a transistor coupled with a capacitor; the capacitor being horizontally offset relative to the transistor; the capacitor and the transistor being in a same planar level as one another; wherein the transistor includes a gate proximate a channel region, and wherein the gate brackets the channel region.