3D Memory Cell Air-Gap Isolation for Reduced Cross-Coupling

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The integration of semiconductor devices is limited by the area occupied by unit memory cells, and existing three-dimensional semiconductor devices face challenges in improving operational reliability and reducing cross-coupling between stacked memory cells.

Innovation Solution

A semiconductor device structure featuring alternately stacked conductive and insulating layers, with air gaps between memory patterns and a sealing layer, and a manufacturing method that includes forming sacrificial patterns, blocking layers, and oxidizing sacrificial liners to create air gaps, which reduces cross-coupling between memory cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If memory cells are stacked in three-dimensional structure to improve integration density, then the area occupied by unit memory cells is reduced, but cross-coupling between stacked memory cells increases and operational reliability deteriorates

Engineering Contradiction:
Improvearea occupied by unit memory cellVSAvoidoperational reliability
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent introduces air gaps that segment the continuous stack structure into isolated sections. These air gaps physically divide the stacked memory cells, preventing electrical interference and cross-coupling between adjacent cells while maintaining the three-dimensional integration architecture. The segmentation allows each memory cell to operate independently, thereby improving reliability without sacrificing integration density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The air gaps act as intermediary elements between stacked memory cells. These gaps serve as insulating mediators that prevent direct electrical interaction between adjacent memory cells, thereby eliminating cross-coupling effects. The intermediary air gaps allow the stacked structure to maintain both high integration density and operational reliability by mediating the interaction between neighboring cells.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If conventional manufacturing methods are used for three-dimensional semiconductor devices, then fabrication processes are simplified, but cross-coupling between memory cells cannot be effectively reduced

Engineering Contradiction:
Improvefabrication process simplicityVSAvoidcross-coupling between memory cells
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent incorporates air gap formation as an early step in the manufacturing process, before subsequent deposition and fabrication steps. By preliminarily creating the air gaps that define the boundaries between memory cells, the process ensures that cross-coupling is prevented from the outset. This preliminary action maintains ease of manufacture while effectively eliminating the harmful cross-coupling effect throughout the remaining fabrication steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent utilizes air gaps as porous/void structures within the stacked memory device. These porous regions (air-filled spaces) provide electrical isolation between memory cells while maintaining structural integrity. The use of air gaps as porous materials allows for effective reduction of cross-coupling without adding complex manufacturing steps, as the air gaps can be formed through standard etching and deposition processes.

Inventive Principle:
Principle #31Porous materials

Data Source

PatentUS11800714B2Semiconductor device and manufacturing method of semiconductor device
Publication Date: 2023.10.24 SK HYNIX INC
  • US11800714B2 patent drawing
  • US11800714B2 patent drawing
  • US11800714B2 patent drawing

AI summary

A semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a channel layer penetrating the gate structure; memory patterns respectively located between the channel layer and the conductive layers; air gaps located between the memory patterns; and a sealing layer including first parts respectively including the air gaps and a second part extending between the memory patterns.