HBM MBIST Architecture for Expanded Memory Testing
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Solution Overview
Problem
The challenge of implementing additional memory devices in high-bandwidth memory (HBM) systems is the spatial constraints and inefficiencies in testing and routing schemes, particularly due to the high routing density and lack of space for direct interconnects between the processor and additional memory devices.
Innovation Solution
The solution involves relocating memory controllers and standard compliant PHYs onto the HBM device's interface die, incorporating an MBIST engine to test the operability of the HBM device and additional memory devices, and using a high-bandwidth interconnect to facilitate communication between the processor and memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional memory devices are added to increase storage capacity, then storage capacity is improved, but spatial constraints and routing density worsen
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture using through-silicon vias (TSVs). Memory devices are stacked vertically above the HBM device, allowing additional storage capacity to be added in the vertical dimension rather than consuming horizontal space on the substrate. This enables increased storage capacity while maintaining substrate area constraints.
2Device complexity
If memory controllers and PHYs are integrated onto the interface die, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent integrates multiple functional components (memory controllers and standard-compliant PHYs) onto the same interface die that already contains the HBM physical layer. This consolidation eliminates the need for separate dedicated controller dies and reduces routing complexity by shortening interconnect paths. The integration is achieved through standard semiconductor fabrication processes that form TSVs and conductive structures during normal manufacturing.
Solution Approach 2:
The interface die is designed to perform multiple functions: it contains the HBM physical layer for high-speed communication, memory controllers for managing memory operations, and standard-compliant PHYs for interfacing with additional memory devices. This multi-functional interface die serves as a universal platform that handles both HBM and standard memory protocols, reducing the need for separate specialized components.
3Quantity of substance
If through-silicon vias are used for vertical integration, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension through through-silicon vias to stack memory devices above the HBM device, enabling increased storage capacity without expanding the substrate footprint. The TSVs provide direct vertical interconnects that simplify routing compared to lateral connections, as they eliminate the need for complex multi-layer trace routing across the substrate.
Solution Approach 2:
The interface die acts as an intermediary between the processor and the stacked memory devices. It contains the memory controllers that manage communications with both the HBM device and additional standard memory devices, simplifying the overall system architecture by centralizing control functions on a single die rather than requiring direct processor connections to multiple memory types.
4Device complexity
If a single MBIST engine is used to test multiple memory devices, then device complexity is reduced, but testing time increases
Solution Approach 1:
The MBIST engine is designed as a universal testing platform that can test multiple types of memory devices (HBM device and additional standard memory devices) through a single integrated interface. It generates appropriate test patterns and interprets results for different memory types, eliminating the need for separate dedicated test engines for each memory device type.
Solution Approach 2:
The MBIST engine dynamically adapts its testing sequence and methodology based on the target memory device being tested. It can switch between testing HBM memory and standard memory devices, adjusting test parameters and patterns accordingly. This dynamic flexibility allows a single engine to efficiently test multiple device types without requiring static dedicated hardware for each memory type.
Data Source
AI summary
This present invention relates to an HBM device with an MBIST engine. The HBM device includes a logic die and one or more memory dies. The logic die includes an HBM PHY configured to communicate signaling between a processor and the one or more memory dies, a separate die-to-die interface configured to communicate signaling between the processor and a memory controller, and the memory controller configured to communicate signaling between the die-to-die interface and one or more additional memory dies separate from the HBM device. The MBIST engine is also located on the logic die. The MBIST engine is coupled with the one or more memory dies and the memory controller and configured to operate a testing procedure on the one or more memory dies and the memory controller. In doing so, the MBIST engine can test the operability of the HBM device.