3D Memory Cell Structure for Higher Density and Lower Parasitics
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Solution Overview
Problem
Existing memory devices face challenges in increasing net die density due to structural limitations, which hinder the reduction of parasitic capacitance and enhancement of capacitance in shrunken memory cells.
Innovation Solution
A memory device with a 3D structure is developed, featuring vertically stacked active layers, bit lines, capacitors, and word lines, including a fin channel layer covered by a word line protrusion, to enhance cell density and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell is shrunk to increase net die, then parasitic capacitance decreases and capacitance increases, but structural limitations prevent further increase in net die
Solution Approach 1:
The patent transitions from planar 2D memory cell structures to three-dimensional vertical structures. Multiple active layers are stacked vertically along a first direction, with word lines extending along side surfaces of active layers. This vertical stacking enables higher cell density without further shrinking the horizontal footprint, resolving the structural limitations that prevented net die increase.
Solution Approach 2:
The patent implements nested structures where word lines are positioned to wrap around or cover fin channel layers that extend from active layers. The word lines include protrusions that cover the fin channel layers, creating a nested configuration where control gates envelop the channel regions, enabling triple-gate control and improved transistor performance within compact volumes.
2Object-affected harmful factors
If memory cell is shrunk, then parasitic capacitance decreases, but capacitance increase is limited by structural constraints
Solution Approach 1:
By stacking multiple active layers vertically, the patent reduces the horizontal dimensions of individual cells while maintaining or increasing total capacitance through the cumulative effect of multiple stacked capacitors. The vertical arrangement allows parasitic capacitance to decrease due to smaller planar footprint while total capacitance increases through stacking.
Solution Approach 2:
The patent combines multiple memory cell components into vertically integrated structures. Multiple active layers, capacitors, and word lines are merged into a single vertical stack, allowing the cell to achieve higher capacitance in a compact volume while minimizing parasitic capacitance through reduced lateral spacing.
3Quantity of substance
If vertically stacked structure is implemented, then cell density increases, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary patterning actions where sacrificial layers are formed first, followed by sequential deposition and etching steps to create the vertical stack. Word lines are formed to extend along side surfaces of active layers in predetermined positions, enabling self-aligned fabrication that reduces manufacturing complexity despite the three-dimensional structure.
Solution Approach 2:
The manufacturing process is segmented into discrete sequential steps: forming sacrificial layers, depositing active layer materials, creating word line structures, and removing sacrificial layers. This segmentation of the fabrication process into manageable stages reduces overall manufacturing complexity while achieving high cell density through vertical stacking.
4Reliability
If word line includes protrusion covering fin channel layer, then triple gate control is achieved, but device structure becomes more complex
Solution Approach 1:
The word line structure is designed with protrusions that nest around the fin channel layers, creating a triple-gate configuration where the gate electrode envelops the channel from multiple sides. This nested geometry provides superior electrostatic control and current characteristics while maintaining a compact structure that integrates seamlessly into the vertical stack.
Solution Approach 2:
The word line transitions from a simple planar structure to a three-dimensional structure with protrusions that extend vertically to cover the fin channel layers. This dimensional transformation enables triple-gate control by wrapping the gate around the channel in multiple directions, improving reliability through enhanced electrostatic control.
Data Source
AI summary
The disclosure relates to a highly integrated memory device and a method for manufacturing the same. According to the disclosure, a memory device comprises a lower structure, an active layer horizontally oriented parallel to a surface of the lower structure, a bit line connected to a first end of the active layer and vertically oriented from the surface of the lower structure, a capacitor connected to a second end of the active layer, a word line horizontally oriented to be parallel with the active layer along a side surface of the active layer, and a fin channel layer horizontally extending from one side surface of the active layer, wherein the word line includes a protrusion covering the fin channel layer.