Memory Cell Void Structure for Reduced Capacitive Coupling
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Solution Overview
Problem
In memory architectures like ferroelectric random access memory (FeRAM), there is a challenge in reducing the capacitance between adjacent memory cells to improve operational efficiency, as large capacitance can lead to undesirable coupling during memory operations.
Innovation Solution
The introduction of voids between adjacent columns of memory cells, achieved by forming sacrificial structures and removing them using a selective wet etch process, reduces capacitance by filling the voids with a substance like air, which has a low dielectric constant, thereby minimizing coupling between electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are placed adjacent to each other in a dense array, then memory device density is improved, but capacitance coupling between adjacent memory cells increases
Solution Approach 1:
A dielectric material is introduced as an intermediary substance between adjacent memory cell electrodes. This dielectric layer acts as a mediator that reduces the capacitance coupling between electrodes while allowing the memory cells to remain in close proximity, thus maintaining high density while minimizing harmful capacitive interference.
Solution Approach 2:
The capacitance between adjacent memory cells is reduced by changing the dielectric properties of the material between electrodes. By selecting materials with appropriate dielectric constants or by adjusting the thickness of dielectric layers, the capacitance parameter is optimized to reduce coupling while maintaining device density.
2Length of moving object
If the distance between adjacent memory cells is reduced, then memory device density is improved, but the capacitance between electrodes increases leading to undesirable coupling
Solution Approach 1:
A dielectric material is introduced as an intermediary substance between adjacent memory cell electrodes. This dielectric layer acts as a mediator that reduces the capacitance coupling between electrodes while allowing the memory cells to remain in close proximity, thus maintaining high density while minimizing harmful capacitive interference.
Solution Approach 2:
The capacitance between adjacent memory cells is reduced by changing the dielectric properties of the material between electrodes. By selecting materials with appropriate dielectric constants or by adjusting the thickness of dielectric layers, the capacitance parameter is optimized to reduce coupling while maintaining device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces capacitance between memory cells, enhancing the efficiency of memory operations and preventing undesirable coupling, thus improving the performance of FeRAM architectures.
Implementation Method 1
forming sacrificial structures and removing them using a selective wet etch process
Implementation Method 2
reduces capacitance by filling the voids with a substance like air, which has a low dielectric constant, thereby minimizing coupling between electrodes
Data Source
AI summary
Methods, systems, and devices for memory structures with voids are described. A memory architecture may include voids between adjacent columns of memory cells. For example, a memory array may be manufactured by forming one or more sacrificial structures, as well as a liner material on sidewalls of the sacrificial structures, extending in the column direction. Memory cells may be formed on the sacrificial structures by patterning a conductive material to form bottom electrodes, forming a ferroelectric material adjacent to the bottom electrodes, and forming a set of plate lines over the ferroelectric material. The sacrificial structures may then be removed to form voids between at least some adjacent columns of memory cells.