Voltage Supply Circuit With Dual Regulators for Standby Interference Control
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Solution Overview
Problem
Low drop-out regulators (LDOs) face challenges in minimizing the influence of standby voltage regulators on active mode operations due to their slow response, requiring a solution to manage target voltage settings effectively.
Innovation Solution
A voltage supply circuit with a signal generation circuit to generate enable signals, an active voltage regulator, and a standby voltage regulator, along with a voltage comparator and input/output controllers, to manage voltage levels dynamically based on mode transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the standby voltage regulator operates in standby mode with a slow response, then power consumption is reduced, but it cannot quickly adjust voltage when transitioning to active mode
Solution Approach 1:
The patent implements dynamic switching between standby and active voltage regulators based on operational mode. The standby regulator operates at low power during idle periods, while the active regulator takes over during active mode to provide fast response. This dynamic configuration resolves the contradiction by allowing the system to optimize for power consumption during standby and for response speed during active operation.
Solution Approach 2:
The patent maintains the active voltage regulator in a pre-configured state during standby mode, ready to immediately take over when needed. This preliminary preparation ensures that when mode transition occurs, the active regulator can instantly provide the required voltage without delay, while the standby regulator continues to conserve power.
2Stability of the object's composition
If the standby voltage regulator maintains a high target voltage, then voltage stability is improved, but it interferes with active mode operations requiring lower voltage
Solution Approach 1:
The patent divides the voltage regulation function into two separate regulators: a standby voltage regulator that maintains stable high voltage for standby mode, and an active voltage regulator that provides adaptable voltage levels for active mode operations. This segmentation allows each regulator to be optimized for its specific mode without interference, resolving the contradiction between voltage stability and mode adaptability.
Solution Approach 2:
The patent introduces a mode selection circuit as an intermediary that controls which voltage regulator is active based on the operational state. This mediator ensures that the standby regulator's high voltage output does not interfere with active mode operations by selectively enabling the appropriate regulator, thus maintaining both voltage stability in standby and adaptability in active mode.
3Device complexity
If a single voltage regulator is used for both standby and active modes, then device complexity is reduced, but it cannot simultaneously optimize for both modes
Solution Approach 1:
The patent segments the voltage regulation system into dedicated standby and active regulators, each optimized for their specific operational mode. This segmentation improves reliability by ensuring that each regulator performs its specialized function without compromise, while the overall complexity is managed through systematic design and control circuitry.
Data Source
AI summary
The present technology relates to a voltage supply circuit, and the voltage supply circuit according to the present technology includes a signal generation circuit configured to generate an active mode enable signal according to a chip selection signal provided from an external device, and generate a standby mode enable signal using an external voltage provided from the external device, an active voltage regulator configured to receive the active mode enable signal and output an active mode operation voltage when the active mode enable signal is in a high state, and a standby voltage regulator configured to receive the active mode enable signal and the standby mode enable signal, output a standby mode operation voltage while the standby mode enable signal is in the high state, and output a voltage lower than the standby mode operation voltage when the active mode enable signal is in the high state.