Underground Interconnect Structure for Compact Source-Drain Routing
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Solution Overview
Problem
Current integrated circuits face challenges in reducing area, power consumption, and noise due to large source or drain diffusion areas required for connecting metal wires, which increases capacitance and complicates chip design as dimensions shrink, making it difficult to achieve efficient signal transfer and scaling.
Innovation Solution
A semiconductor device structure with underground interconnections embedded in a silicon substrate, allowing for compact self-aligned connections to source or drain, reducing the need for surface area and optimizing isolations, thereby enhancing transistor and circuit performance by distributing signal sources and voltages vertically within the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal wires are connected to source or drain through contact holes and connection plugs, then signal transfer is enabled, but the source or drain diffusion area must be enlarged to accommodate photolithographic misalignment, which increases area consumption and capacitance
Solution Approach 1:
The patent moves the interconnection from the traditional planar surface (above the silicon substrate) to an underground dimension (embedded in the silicon substrate). This dimensional change allows the interconnection to be formed below the surface, eliminating the need for large surface diffusion areas and reducing the area penalty associated with contact holes and alignment margins.
Solution Approach 2:
Instead of connecting interconnections to source or drain from above through contact holes, the patent inverts the approach by forming underground interconnections that connect from below. The interconnection is embedded in the silicon substrate and connects to the source or drain region from the opposite direction, eliminating the need for traditional contact hole structures.
2Manufacturing precision
If source or drain diffusion area is enlarged to ensure contact hole alignment, then manufacturing robustness is improved, but capacitance increases and power consumption rises
Solution Approach 1:
By transitioning from surface-level connections to subsurface embedded interconnections, the patent eliminates the need for large diffusion areas used for alignment margins. The underground interconnection is formed at a depth where alignment constraints are relaxed, thereby reducing the diffusion area and the associated capacitance and power consumption.
Solution Approach 2:
The patent extracts the interconnection structure from the traditional surface contact hole approach and relocates it to an underground embedded position. This extraction removes the dependency on large surface diffusion areas for alignment purposes, directly reducing the area and capacitance penalties.
3Adaptability or versatility
If multiple interconnection layers are stacked above the silicon surface to distribute signals and power, then signal routing capability is improved, but device complexity and contact area increase
Solution Approach 1:
The patent utilizes the vertical dimension below the silicon surface to embed interconnections, providing an additional routing space that does not increase lateral complexity. By distributing interconnections at different depths underground, the patent achieves versatile signal routing without stacking multiple layers above the surface, thereby reducing contact area and simplifying the overall device structure.
Solution Approach 2:
The patent embeds interconnection structures within the silicon substrate, nesting them at different vertical levels below the surface. This nested arrangement allows multiple interconnection paths to coexist within the substrate volume, providing routing versatility without increasing the lateral footprint or requiring complex stacked layers above the surface.
Data Source
AI summary
A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.