Pass Transistor Circuit Layout for Memory Leakage Isolation
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Solution Overview
Problem
Existing memory devices face challenges in managing leakage currents and voltage interference between pass transistors due to the proximity of gate electrodes, which can affect the integrity and efficiency of memory operations.
Innovation Solution
The memory device incorporates a design with recessed portions and protrusions in the active areas of pass transistors, allowing for increased spacing between gate electrodes and reducing the influence of high voltages, thereby minimizing leakage currents and improving operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate electrodes of pass transistors are placed close to each other to increase integration density, then device complexity is reduced and productivity is improved, but leakage currents increase and voltage interference occurs between adjacent transistors
Solution Approach 1:
The active area is designed with different local geometries: a narrow portion where the gate electrode is positioned and wider portions at the ends. This local variation in width allows the gate electrodes to be closely spaced for high density while maintaining adequate separation between the drain/source regions of adjacent transistors, preventing leakage currents and voltage interference.
2Reliability
If gate electrodes are spaced far apart to reduce leakage currents and voltage interference, then reliability is improved, but integration density decreases and device complexity increases
Solution Approach 1:
The active area employs non-uniform width distribution with narrow sections under the gate and wider sections at the terminals. This allows adjacent transistors to share common diffusion regions in the narrow portions (increasing density) while maintaining sufficient isolation in the wider terminal portions (reducing leakage and interference).
Solution Approach 2:
Adjacent pass transistors share common source/drain diffusion regions in the narrow portions of the active area. This merging of regions reduces the total area required for multiple transistors while the gate electrode structure maintains electrical isolation, achieving high integration density without sacrificing reliability.
Data Source
AI summary
A memory device including a substrate having a first active area and a second active area adjacent to each other in a first horizontal direction is disclosed. A first pass transistor is disposed on the substrate and has a first gate electrode crossing the first active area in the first horizontal direction, and a second pass transistor is disposed on the substrate and has a second gate electrode crossing the second active area in the first horizontal direction. The first active area has, in a planar view, a first recessed portion facing the second gate electrode on one side adjacent to the second active area.