Current Mirror Circuit Layout for Bus Voltage Drop Isolation
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Solution Overview
Problem
Current mirror circuits in semiconductor integrated circuits face errors in generated mirror currents due to parasitic resistance in the power supply bus, especially when the driver device and mirror devices are located at significant distances apart, leading to unacceptable variations in current values.
Innovation Solution
The implementation of current mirror circuits that utilize additional transistors to isolate the gate-to-source voltage of mirror devices from voltage drops in the power supply bus, ensuring that mirror currents are proportional to the reference current independent of distance and voltage differences, by using a quiet ground or power bus to maintain consistent voltages across all instances of mirror devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the driver device and mirror devices share a common power supply bus, then the circuit structure is simple, but parasitic resistance in the power supply bus causes errors in the generated mirror current
Solution Approach 1:
The patent divides the power supply connection into two separate paths: a first power supply bus for the driver device and a second power supply bus for the mirror devices. This segmentation isolates the mirror devices from the parasitic resistance of the first power supply bus, allowing accurate current mirroring even when the driver and mirror devices are far apart on the chip.
Solution Approach 2:
The patent introduces a compensation circuit as an intermediary element that measures the voltage drop across the parasitic resistance and generates a compensating signal. This compensation circuit acts as a mediator between the power supply bus and the mirror devices, correcting for the voltage errors caused by parasitic resistance without requiring a complete redesign of the power distribution network.
2Adaptability or versatility
If the distance between driver device and mirror device is significant, then the circuit can be distributed across the chip, but voltage drops due to parasitic resistance cause errors in mirror current
Solution Approach 1:
The patent segments the power supply network into dedicated first and second power supply buses, allowing the driver and mirror devices to be physically distributed across the chip while maintaining electrical isolation. This enables large-scale integration with many mirror devices far from the driver without compromising current accuracy.
Solution Approach 2:
The patent implements a feedback mechanism where the compensation circuit continuously monitors the voltage drop caused by parasitic resistance and adjusts the mirror device operating point accordingly. This feedback loop maintains accurate current mirroring despite variations in distance and loading conditions across the distributed chip layout.
3Manufacturing precision
If additional transistors are added to isolate gate-to-source voltage from voltage drops, then mirror current accuracy is improved, but device complexity increases
Solution Approach 1:
The patent introduces a compensation circuit with additional transistors as an intermediary system that mediates between the power supply variations and the mirror devices. These additional transistors form a compensation network that actively counteracts the effects of parasitic resistance, providing high-precision current mirroring despite the increased device count.
Solution Approach 2:
The patent changes the operating parameters of the mirror devices by using the compensation circuit to adjust gate voltages and bias conditions. This parameter adjustment compensates for voltage drops in the power supply network, maintaining accurate current mirroring ratios even with the additional complexity of the compensation circuitry.
Data Source
AI summary
A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output terminal of the circuit, the second terminal of the second transistor is coupled to the power supply bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current substantially independent of distance between the first transistor and the second transistor.