Voltage Reference Circuit With Bulk Feedback for Stable Low-Power Output
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Solution Overview
Problem
Existing voltage reference circuits are susceptible to variations in supply voltage and temperature, consume high power, and require native nMOS transistors, limiting their applicability in technologies like FDSOI.
Innovation Solution
A voltage reference circuit using three transistors in a stacked configuration with a regulating transistor connected to the output node for feedback, maintaining a stable reference voltage level by compensating for parameter fluctuations, and utilizing input/output transistors to avoid native nMOS requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a 2T voltage reference circuit using native nMOS transistor is used, then the circuit area is compact, but the circuit is susceptible to supply voltage variations and requires native nMOS transistors which are not available in all technologies
Solution Approach 1:
The patent implements a feedback mechanism where the bulk terminal of the regulating transistor is connected to the output node, creating a negative feedback loop that automatically compensates for supply voltage variations. When the supply voltage changes, the feedback through the bulk terminal adjusts the transistor operation to maintain a stable reference voltage, thereby improving insensitivity to supply voltage variations while maintaining compact area.
2Reliability
If additional transistors are added to improve supply voltage insensitivity, then the insensitivity to supply voltage improves, but the device complexity and power consumption increase
Solution Approach 1:
The regulating transistor in the patent serves multiple functions simultaneously: it regulates the reference voltage output, provides feedback compensation through its bulk terminal connection, and operates within the stacked transistor configuration to maintain low power consumption. This multi-functionality allows the circuit to achieve improved supply voltage insensitivity without proportionally increasing device complexity.
3Stability of the object's composition
If the voltage reference circuit is always-on to provide continuous reference voltage, then the reference voltage stability is maintained, but the power consumption becomes significant in sleep-mode devices
Solution Approach 1:
The patent employs parameter changes by operating the transistors in the subthreshold region, where small changes in gate or bulk voltage produce exponential changes in current. This allows the circuit to achieve stable reference voltage output while operating at extremely low current levels, thereby maintaining reference voltage stability without significant power consumption in sleep-mode devices.
4Ease of manufacture
If native nMOS transistors are used in the voltage reference circuit, then the circuit can be implemented with compact architecture, but the circuit cannot be implemented in technologies like FDSOI where only native pMOS transistors are available
Solution Approach 1:
The patent inverts the conventional approach by using the bulk terminal connection in a non-traditional manner. Instead of relying on native nMOS transistors with specific substrate connections, the invention connects the bulk terminal of the regulating transistor to the output node, creating a technology-agnostic solution that works with available transistor types (including FDSOI with native pMOS) while maintaining compact architecture through the stacked transistor configuration.
Data Source
AI summary
A voltage reference circuit comprises: a first transistor; a second transistor, wherein the first transistor and the second transistor are arranged in a stacked connection between a terminal connected to ground and a terminal connected to a supply voltage, wherein a reference voltage is output at an output node between the first transistor and the second transistor; and a regulating transistor, wherein the regulating transistor is connected between the supply voltage and the first transistor in a stacked connection with the second transistor, wherein a bulk terminal of the regulating transistor is connected to the output node for compensating changes in the reference voltage at the output node to maintain a stable reference voltage level.