Segmented Power Gate Clamping for Data Retention and Noise Control
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Solution Overview
Problem
Conventional methods for data retention during sleep mode in handheld devices face challenges such as data loss and performance degradation due to destructive sleep modes, and they also introduce supply noise in neighboring circuits, leading to long wake-up latencies and area overhead.
Innovation Solution
The solution involves using a single retention voltage for all circuits, with a primary power gate transistor and secondary power gate transistors that are larger in size, allowing for controlled clamping modes to mitigate supply noise and reduce wake-up latency, while reusing existing power gates to minimize area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional destructive sleep mode is used to reduce leakage power, then power consumption is reduced, but data loss occurs and wake-up latency increases
Solution Approach 1:
The power gate transistor is divided into multiple segments (first power gate transistor and second power gate transistor) that can be independently controlled. This segmentation allows the circuit to be placed in different sleep modes (destructive sleep, retentive sleep, or active mode) without requiring full wake-up, thereby reducing wake-up latency while maintaining leakage power reduction benefits.
Solution Approach 2:
The patent implements dynamic power management by allowing the power gate to transition between multiple operational states (fully on, fully off, or partially off with retentive sleep). The control logic dynamically selects the appropriate mode based on whether data retention is needed, enabling flexible trade-off between power savings and wake-up speed.
2Loss of energy
If conventional destructive sleep mode is used to reduce leakage power, then power consumption is reduced, but data loss occurs
Solution Approach 1:
The power gate is segmented into controllable portions that can independently manage different circuit blocks. This allows selective application of destructive sleep to non-critical circuits while maintaining retentive sleep or active mode for circuits requiring data retention, thus achieving overall power reduction without data loss in critical paths.
Solution Approach 2:
Different regions of the circuit are assigned different power modes based on their data retention requirements. Critical circuits maintaining data use retentive sleep or active mode, while non-critical circuits use destructive sleep, creating localized quality differences in power management strategy.
3Loss of time
If fast wake-up is implemented to reduce wake-up latency, then wake-up time is reduced, but supply noise increases in neighboring circuits
Solution Approach 1:
The power gate segmentation enables selective wake-up of only the necessary circuit segments rather than waking up the entire power domain. This reduces the overall wake-up latency while limiting the supply noise generation to only the specific segments that are being activated, protecting neighboring circuits from excessive noise.
4Reliability
If multiple power gates are added to enable retentive sleep modes, then data retention capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the functionality of multiple power gates into a unified segmented power gate structure where the first and second power gate transistors work together under coordinated control. This combining approach achieves data retention capability without proportionally increasing device complexity, as the segmented gates share control logic and can be implemented within existing process technologies.
Data Source
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AI summary
An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.