Phase Change Memory Interconnect Layout for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need to improve electronic chips comprising memory circuits based on phase change materials, particularly in terms of manufacturing processes and integration with semiconductor substrates.
Innovation Solution
The solution involves a semiconductor substrate with selection transistors, interconnection stacks, and memory cells using phase change material resistive elements, connected via conductive vias and tracks, with a unique third insulating layer enhancing connectivity and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If phase change memory cells are integrated with semiconductor substrates using conventional interconnection methods, then manufacturing compatibility is maintained, but parasitic capacitance increases and connectivity efficiency decreases
Solution Approach 1:
The patent introduces a third insulating layer that extends vertically over the interconnection stacks, creating a new dimensional space for routing conductive vias. This vertical dimension allows direct connections between memory cells and logic circuits without increasing lateral footprint, thereby reducing parasitic capacitance while maintaining manufacturing compatibility.
Solution Approach 2:
The third insulating layer acts as an intermediary structure that facilitates clean electrical isolation between the interconnection stacks and the new conductive vias. This mediator layer enables efficient connectivity by providing a dedicated pathway that minimizes capacitive coupling between adjacent conductors.
2Reliability
If conventional interconnection stacks are used for connecting memory cells, then manufacturing processes remain simple, but connectivity efficiency and signal integrity deteriorate
Solution Approach 1:
The interconnection structure is segmented into distinct functional layers: conventional interconnection stacks for lateral routing and a third insulating layer with vertical vias for through-connectivity. This segmentation allows each layer to be optimized for its specific function while maintaining compatibility with existing manufacturing processes.
Solution Approach 2:
By adding the vertical dimension through the third insulating layer, the patent creates short, direct via connections that improve signal integrity and reduce parasitic effects, while the manufacturing process remains compatible with standard semiconductor fabrication techniques.
3Productivity
If memory cells are directly integrated on semiconductor substrate, then device density increases, but parasitic capacitance and interference increase
Solution Approach 1:
The third insulating layer serves as an intermediary isolation structure between densely packed memory cells and logic circuits. This mediator provides electrical separation that reduces parasitic capacitance and signal interference, enabling high device density without compromising signal integrity.
Solution Approach 2:
The patent applies different dielectric properties locally: the third insulating layer uses material with higher dielectric constant for isolation in specific regions, while maintaining lower loss characteristics in signal path regions. This local optimization reduces parasitic effects while preserving high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves connectivity and reduces parasitic capacitance, enabling efficient integration of phase change memory cells while maintaining compatibility with existing manufacturing methods and logic circuits.
Implementation Method 1
A phase change material is a material that has the ability to change its crystalline state under the effect of heat, and more specifically to switch between a crystalline state and an amorphous state
Data Source
Figure 1A~1B
Figure 2A~2C
Figure 2D~2E
AI summary
The present description relates to an electronic device (11) comprising: - a semiconductor substrate (13) in which selection transistors are arranged; - a first interconnection stack (35) comprising at least one level comprising first and second insulating layers (37, 39), in which conductive tracks (71) and first conductive vias (69) are defined; - a third insulating layer (45), resting on the first stack; - a second interconnection stack (36), comprising at least one level comprising first and second insulating layers (37, 39); - a plurality of memory cells (M) arranged in the third insulating layer (45); and - at least one second conductive via (70) extending over the entire height of the third insulating layer.