Drain-Ballasted ESD Circuit for Bidirectional High-Voltage Protection
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Solution Overview
Problem
Existing electrostatic discharge (ESD) protection circuits in integrated circuits (ICs) are inadequate for higher voltage domains, as they exhibit unidirectional protection, significant 'overshoot' effects, and high initiation voltages, leading to potential damage and inefficient use of space, which limits their scalability and performance.
Innovation Solution
The implementation of a drain-ballasted electrostatic discharge protection circuit that couples two voltage domains using back-to-back n-type metal-oxide-semiconductor (NMOS) transistors with a grounding resistor, providing bi-directional protection with minimal 'overshoot' and low initiation voltage, suitable for higher voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional ESD protection circuits are used in higher voltage domains, then the circuit can operate at higher voltages, but the protection becomes unidirectional and exhibits significant overshoot effects
Solution Approach 1:
The patent employs back-to-back NMOS transistors configured in an asymmetric arrangement where each transistor's source connects to one voltage domain and drain to the other, creating a symmetric bidirectional protection structure that overcomes the unidirectional limitation of conventional diode-based protectors
Solution Approach 2:
The invention changes the electrical parameters by using NMOS transistors with carefully selected threshold voltages and channel dimensions to achieve low initiation voltage and minimal overshoot, replacing the fixed parameters of conventional diode structures
2Device complexity
If conventional ESD protection circuits are used, then the circuit structure is simple, but the protection exhibits high initiation voltage and significant overshoot effects
Solution Approach 1:
The patent introduces an intermediate resistive element connected to the drain of each NMOS transistor that acts as a ballast resistor, controlling the current flow and reducing the overshoot effect while maintaining a relatively simple circuit structure
Solution Approach 2:
The invention replaces the passive diode-based protection mechanism with an active transistor-based system that can dynamically control the protection characteristics, substituting a static mechanical-like structure with a controllable electronic system
3Area of stationary object
If conventional ESD protection circuits are used, then the circuit occupies less space, but the protection is inadequate for higher voltage domains
Solution Approach 1:
The patent designs a universal ESD protection structure using standard NMOS transistors and resistors that can be integrated into higher voltage domains while maintaining compact footprint, making the same basic structure applicable across different voltage domains
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively mitigates ESD events across higher power voltage domains, enhancing the performance of computing systems by providing robust and compact ESD protection without significant space occupancy.
Implementation Method 1
a grounding resistor coupled to the first NMOS transistor (e.g., to a first gate of a NMOS transistor) and the second NMOS transistor (e.g., to a second gate of a NMOS transistor) to increase the electrical resistance of each of the respective drains of the NMOS transistors
Implementation Method 2
Drain-ballasted electrostatic discharge protection circuits... effectively mitigates ESD events across higher power voltage domains
Data Source
AI summary
An apparatus includes a first voltage domain including a first circuit configured to operate at a first supply voltage, a second voltage domain including second circuit configured to operate at a second supply voltage, and a drain-ballasted electrostatic discharge (ESD) protection circuit configured to electrically couple the first voltage domain and the second voltage domain, the drain-ballasted ESD protection circuit including a first NMOS transistor, a second NMOS transistor, a floating interconnect that electrically couples the first NMOS transistor to the second NMOS transistor, and a grounding resistor coupled to the first NMOS transistor and the second NMOS transistor.