Memory Power Gating Circuit for Faster Retention Wake-Up
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power gating circuits in memory systems face challenges in achieving fast wake-up from retention mode due to the dominance of precharging the core array power supply from a diode drop voltage, which is a significant component of the wake-up time.
Innovation Solution
A power gating circuit design that allows transistors to be reconfigured between diode and transistor modes, using a selection device to control the gate connection, enabling faster precharge and wake-up by converting diodes to transistors during the wake-up sequence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If diodes are used to provide reduced power supply through power gating circuit, then leakage is reduced, but wake-up time increases due to slow precharge from diode drop voltage
Solution Approach 1:
The patent applies dynamics by making the transistor configuration changeable between diode mode and transistor mode based on operational requirements. The selection device dynamically reconfigures the transistors: in normal operation, transistors are configured as diodes to reduce leakage; during wake-up sequence, they are reconfigured as transistors to enable fast precharge. This dynamic reconfiguration resolves the contradiction between leakage reduction and wake-up speed.
Solution Approach 2:
The patent changes the electrical parameters of the power gating circuit by switching between diode configuration (higher voltage drop, lower leakage) and transistor configuration (lower voltage drop, higher drive strength). The selection device controls the gate voltage of the transistors to achieve parameter changes: connecting gate to drain creates diode configuration with ~0.7V drop; connecting gate to appropriate voltage line creates transistor configuration with full drive strength, enabling fast precharge during wake-up.
2Speed
If transistors are used in power gating circuit, then drive strength is high for fast precharge, but leakage increases compared to diode configuration
Solution Approach 1:
The patent uses dynamics to switch between transistor mode (for fast precharge) and diode mode (for low leakage) based on operational phase. The selection device enables the circuit to be in transistor configuration only during wake-up sequence when fast precharge is needed, and switches to diode configuration during normal operation to minimize leakage. This temporal separation resolves the contradiction between speed and energy loss.
Solution Approach 2:
The patent applies periodic action by using the power gating circuit in different modes at different times: diode mode during normal standby operation for leakage reduction, and transistor mode during periodic wake-up sequences for fast precharge. The selection device orchestrates this periodic switching between modes, allowing the system to optimize for leakage most of the time while enabling fast wake-up when needed.
Data Source
AI summary
A power gating circuit for a memory includes a plurality of header switches, the plurality of header switches comprising: a first transistor having a source tied to an external power supply line; and a second transistor coupled to a drain of the first transistor and having its own drain coupled to an internal voltage line of the memory, wherein the second transistor is structured to be used as a transistor or a diode based on control of a gate of the second transistor; and a selection device coupled to the gate of the second transistor to controllably couple the gate of the second transistor in a first state to the drain of the second transistor for diode operation and in a second state to a second voltage line for transistor operation.