3D Horizontal DRAM Cell Stacking for Higher Circuit Density
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Solution Overview
Problem
The challenge in semiconductor device fabrication is to increase transistor density beyond the limitations of two-dimensional (2D) circuits, as scaling to single-digit nanometer nodes faces significant challenges, and existing methods struggle with the complexity of stacking transistors and capacitors in three-dimensional (3D) integration, especially for logic chips like CPUs and GPUs.
Innovation Solution
A method for fabricating a semiconductor structure involving the formation of stacked horizontal 3D DRAM cells using silicon nanosheet transistors and highly doped Si capacitors, with a gate-all-around configuration and common ground connection for metal plates, allowing for vertical stacking while maintaining high performance and circuit density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are created in one plane with wiring formed above (2D circuits), then manufacturing process is simpler, but transistor density per unit area is limited
Solution Approach 1:
The patent transitions from two-dimensional planar circuits to three-dimensional vertically stacked circuits. Multiple transistor layers are stacked vertically with alternating doping types (n-type and p-type), enabling higher transistor density by utilizing the vertical dimension. The wiring and interconnect structures are also extended into the vertical dimension to connect the stacked transistor layers, resolving the density limitation of 2D layouts.
2Length of moving object
If scaling enters single digit nanometer nodes, then transistor size is reduced, but fabrication challenges increase significantly
Solution Approach 1:
The patent segments the fabrication process into distinct stages for forming different transistor layers. Each layer is formed through separate deposition, patterning, and doping steps, allowing precise control at single digit nanometer nodes. The vertical stacking is achieved through sequential fabrication of individual transistor layers followed by integration, making the complex 3D structure manufacturable through modular processing.
3Quantity of substance
If vertically stacked transistors are implemented, then circuit density is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple fabrication processes into integrated sequence for forming the vertically stacked transistors. The deposition, patterning, doping, and etching steps for multiple transistor layers are combined and coordinated to achieve the 3D structure. This integrated approach manages the manufacturing complexity by synchronizing the formation of stacked layers with their interconnect structures, enabling high circuit density through coordinated process integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a significant improvement in circuit density by allowing multiple horizontal DRAM cells to be stacked vertically, overcoming the aspect ratio and dielectric constant challenges of conventional vertical stacked DRAM capacitors, achieving high performance and robustness in Idsat and Idoff.
Implementation Method 1
The lower doped semiconductor layer can include a lower doped first-type semiconductor layer and a lower doped second-type semiconductor layer within a transistor area and a capacitor area of the semiconductor structure, respectively
Data Source
AI summary
Aspects of the present disclosure provide a semiconductor structure, which can include a lower transistor including a lower channel that is elongated horizontally and includes a lower doped first-type semiconductor layer of a lower doped semiconductor layer, an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally and includes an upper doped first-type semiconductor layer of an upper doped semiconductor layer, a lower capacitor electrically connected to and horizontally elongated from the lower transistor and including a first lower plate that includes a lower doped second-type semiconductor layer of the lower doped semiconductor layer, and an upper capacitor vertically stacked over the lower capacitor and electrically connected to and horizontally elongated from the upper transistor and including a first upper plate that includes an upper doped second-type semiconductor layer of the upper doped semiconductor layer.