Transistor TRIZ Cases

A floating electrode with T1>T2>T3 oxide thicknesses reshapes the electric field to lower on-resistance while preserving withstand voltage.

Ultra-thin barrier layers and 8-15 nm metal grains cut contact plug resistance in scaled semiconductor source/drain connections.

Vertical source contacts link dense cell arrays to a backside power rail, reducing parasitics to improve speed, reliability, and area use.

Combining polycrystalline and oxide TFTs cuts display power while shared-depth openings simplify fabrication and prevent line shorting.

A trench-filled upper gate and stacked lower gate improve oxide TFT channel control while minimizing oxide semiconductor damage.

Air gaps between adjacent active pillars and word lines lower coupling noise while supporting dense vertical channel memory layouts.

Replacing FET access transistors with a compact BJT array helps shrink RRAM bitcells while maintaining reliable operation.

A bipolar-assisted gate discharge path cuts turn-off time in high-voltage protection switches while limiting overvoltage stress on the load.

Using 3D graphene and biofunctionalization, this BioFET case improves analyte sensitivity in high-salt liquids by reducing ionic screening.

A CMOS-compatible IR-transparent cap hermetically seals MEMS IR sensors in a vacuum cavity, enabling compact, lower-cost detector integration.

Controlled dual MOSFET rectifiers isolate failed converter paths to prevent short circuits while maintaining low-voltage power delivery.

A widened wing trench beneath a buried trench improves manufacturing stability while enabling high- and low-voltage transistors on one chip.

Splitting NMOS fin counts and tuning tensile or compressive stress cuts FinFET leakage 5%-10% while maintaining saturation current.

Surface grooves formed by plasma etching relieve substrate warpage during thinning, lowering drift-layer resistance while protecting yield.

Sn-alloy source, drain, and channel regions tune band gaps in gate-all-around transistors, enabling faster operation without junction complexity.

A semiconductor capping layer separates the gate dielectric from stacked fin layers to prevent threshold shifts and improve transistor reliability.

By moving output circuits, through-vias, and terminals beneath the pixel array, this stacked image sensor cuts terminal area and supports further miniaturization.

A regulator senses voltage at a remote rail point and adjusts the supply node to offset parasitic resistance and stabilize IC power domains.

Early self-aligned gate isolation fins reduce lithography spacing margins, enabling tighter multigate transistor packing and higher IC density.

Recessed sacrificial sidewalls enable epitaxial III-V nanosheet channels on silicon, cutting substrate cost while preserving low-power device performance.

Vertical dielectric protrusions create a 3D transistor channel that cuts footprint while improving drive current, mobility, and power use.

A plateau-guided SiC trench MOSFET structure expands channel width while limiting electric field concentration and improving short-circuit tolerance.

Within-pixel capacitive coupling adds correction data to stored data, enabling HDR image display with lower power and no external conversion circuits.

A buffer channel pattern bridges different stacked MOSFET widths to limit leakage current and preserve reliable electrical characteristics.

A graded backside dopant profile formed by ion implantation and laser annealing lowers contact resistance while limiting leakage from surface scratches.

A lining layer rounds sharp isolation corners so semiconductor contacts form with fewer voids and lower short-circuit risk.

Higher-k dielectric fillers between channel features and the dielectric wall strengthen gate control and cut leakage in fork-sheet FETs.

Hydrogen implant energy is matched to substrate oxygen or carbon levels to control buffer doping and reduce breakdown voltage variation.

A deep anode extending below the trench bottom cuts RC-IGBT recovery loss and forward drop while protecting the trench oxide film.

A two-step weak-then-strong programming sequence prevents over-erase in non-volatile memory cells while improving state switching and power use.

Floating low-resistivity and trap-rich substrate regions cut BiCMOS leakage while preserving NPN yield and RF/FET performance.

A prestressed layer is elastically relaxed near the source and drain to apply tensile channel stress and boost NMOS electron mobility.

Self-aligned lateral trench contacts cut stacked contact layers and resistance in buried power rail layouts, enabling tighter logic and memory cell scaling.

Two depletion regions in series with an anti-punch layer cut SCR ESD capacitance while speeding turn-on and suppressing punch-through.

Backside and frontside contacts with buried power rails solve blocked bottom source/drain access in stacked FETs while reducing flips and misalignment.

A constant-current check detects load shorts before switch turn-on, preventing excessive current and avoiding oversized drivers.

A vertically stacked 2T memory cell cuts footprint limits to raise storage density while preserving read, write, and charge retention.

Vertical flash-like cells compute neural weights in analog form, cutting CMOS circuit complexity while enabling dense, non-volatile arrays.

Hyperabrupt epitaxial junctions raise varicap capacitance while co-fabricating bipolar transistors on one substrate to simplify production.

Air-gap inner spacers and backside rail routing cut gate capacitance and interconnect resistance in scaled multigate ICs.