Ge (111) Vertical FET Channels for Lower Interface State Density
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Solution Overview
Problem
Current semiconductor devices face reduced performance due to high interface state densities in channel surfaces, particularly in III-V semiconductor materials, which impede electron and hole mobility and electrostatic gate control, making high carrier mobility channel materials like Ge (111) more attractive for high-performance applications.
Innovation Solution
The method involves forming crystalline Ge with a hexagonal structure using a Ge condensation process to orient the (111) direction of crystalline Ge vertically in VTFETs, enhancing charge flow and reducing interface state densities, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If III-V semiconductor materials are used for channel surfaces, then carrier mobility is improved, but interface state density increases causing degraded electrostatic gate control
Solution Approach 1:
The patent changes the crystal orientation parameter of the Ge channel from conventional orientations to (111) orientation, which fundamentally alters the interface properties and reduces interface state density while maintaining high carrier mobility
Solution Approach 2:
The patent employs a composite structure combining Ge channel with SiGe source/drain regions and specific spacer materials, creating a multi-material system that optimizes both carrier mobility and electrostatic control by leveraging the advantageous properties of each material
2Speed
If high carrier mobility channel materials like Ge (111) are used, then electron and hole mobility is improved, but device fabrication complexity increases
Solution Approach 1:
The patent performs preliminary Ge condensation into the SiGe fin structures before final device formation, pre-establishing the Ge channel regions with correct orientation and composition, which simplifies subsequent processing steps
Solution Approach 2:
The patent uses SiGe as an intermediary material that facilitates the formation of Ge channel structures. The SiGe fin structures serve as templates and Ge sources, enabling controlled Ge condensation and orientation without requiring direct Ge deposition, thereby simplifying fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with improved electron and hole mobility and electrostatic gate control, offering better performance by aligning the crystalline Ge channel surfaces with the direction of charge flow in VTFETs.
Implementation Method 1
forming crystalline Ge having a hexagonal structure from the SiGe by employing a Ge condensation process to orient a (111) direction of the crystalline Ge in a direction of charge flow for a VTFET
Implementation Method 2
performing an anneal process to diffuse dopants of the first and second bottom source/drain regions
Data Source
AI summary
A method for fabricating a semiconductor device including vertical transport fin field-effect transistors (VTFETs) is provided. The method includes forming a bottom spacer on a first device region associated with a first VTFET and a second device region associated with a second VTFET, forming a liner on the bottom spacer, on a first fin structure including silicon germanium (SiGe) formed in the first device region and on a second fin structure including SiGe formed in the second device region, and forming crystalline Ge having a hexagonal structure from the SiGe by employing a Ge condensation process to orient a (111) direction of the crystalline Ge in a direction of charge flow for a VTFET.