Overlapping M0 Metal Routing for Compact PMOS-NMOS Cell Layouts

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Solution Overview

Problem

Legacy metal routing layer structures in semiconductor packaging face challenges in connecting diffusion contacts between PMOS and NMOS regions due to limited M0 tracks, leading to increased physical area and difficulty in routing misaligned gates or complex logic gates without additional cell growth.

Innovation Solution

A wide center M0 track that spans both PMOS and NMOS regions, allowing for conductivity flexibility and reducing the number of gate pitches required for routing, facilitating smaller standard cell sizes and improved connectivity between PMOS and NMOS devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If legacy metal routing layer structures are used with limited M0 tracks, then routing between PMOS and NMOS regions becomes difficult, but physical area increases and cell growth occurs

Engineering Contradiction:

Improverouting easeVSAvoidcell area

Core Design Contradiction:

Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent allows metal routing tracks to overlap vertically between different routing layers, utilizing the third dimension (vertical stacking) to resolve horizontal routing congestion. This enables connections between PMOS and NMOS regions without increasing lateral cell area, as routes can pass through overlapping tracks in adjacent metal layers rather than requiring additional horizontal space.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If additional devices such as dummy gates are added to accommodate routing, then connectivity between PMOS and NMOS is achieved, but physical area and gate pitches increase

Engineering Contradiction:

Improverouting flexibilityVSAvoiddevice count

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent creates a universal routing infrastructure where metal tracks in different layers can serve multiple routing functions simultaneously. By enabling overlap between M0 and M1 tracks, the same physical space accommodates multiple routing paths, eliminating the need for dedicated dummy gates or additional devices for each connection scenario.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If three M0 signal track architectures are used, then metal track pitch is loosened to lower resistance, but routing difficulty increases due to track scarcity

Engineering Contradiction:

Improveelectrical resistanceVSAvoidrouting ease

Core Design Contradiction:

ReliabilityVSEase of operation

Solution Approach 1:

The patent merges the routing capacity of M0 and M1 layers by allowing their tracks to overlap spatially. This combination effectively doubles the available routing resources in congested areas, providing sufficient track availability for routing while maintaining the loosened pitch configuration that reduces electrical resistance.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20230317602A1Metal routing that overlaps NMOS and PMOS regions of a transistor

Publication Date: 2023.10.05 INTEL CORP

AI summary

Embodiments described herein may be related to apparatuses, processes, and techniques for providing a metal routing layer zero (M0) track within a circuit structure that had a width that overlaps both PMOS and NMOS within the circuit structure. There may be three M0 routing tracks, with a first of the M0 routing tracks directly over PMOS, a second of the M0 routing tracks directly over NMOS, and a third of the M0 routing tracks over a portion separating PMOS and NMOS and overlapping both PMOS and NMOS. The wide second routing track will allow efficient electrical coupling between a device on the PMOS and a device on the NMOS. Other embodiments may be described and/or claimed.