Radiation Imaging Pixel Layout for Low-Crosstalk Shared Readout
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Solution Overview
Problem
Radiation imaging apparatuses face high costs due to expensive IC chips in readout circuits and artifacts in radiation images caused by crosstalk and uneven bias voltage, particularly during high-speed imaging.
Innovation Solution
A radiation imaging apparatus with a two-dimensional matrix of pixels connected to signal lines and bias lines, where adjacent pixels share signal lines and alternate bias sources to reduce wiring capacitance and crosstalk, thereby minimizing artifacts and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple IC chips are used in the readout circuit to maintain high-density integration of analog amplifiers and A/D converters, then the imaging apparatus can achieve high-resolution radiation imaging, but the cost of the imaging apparatus increases significantly
Solution Approach 1:
The patent merges the readout circuits for adjacent pixels by sharing common signal lines. Specifically, pixels arranged in a two-dimensional matrix share signal lines in a column direction, allowing multiple pixels to be read out through fewer IC chips. This reduces the total number of IC chips required while maintaining the ability to read out signals from all pixels, thereby reducing cost while preserving imaging resolution.
2Device complexity
If signal lines are shared between adjacent pixels to reduce the number of IC chips, then the cost decreases, but crosstalk between pixels increases causing artifacts in radiation images
Solution Approach 1:
The patent applies different connection configurations to different pixels based on their positions. Pixels are divided into groups where adjacent pixels share signal lines, but the connection direction and bias line assignment are optimized locally to minimize crosstalk. Specifically, pixels in the same row but different columns are connected to different bias lines, creating localized differentiation that reduces interference while maintaining shared signal line benefits.
Solution Approach 2:
The patent segments the pixel array into groups that share common signal lines and bias lines. By organizing pixels in a two-dimensional matrix and assigning shared signal lines to columns, the system creates segmented readout paths that reduce the total number of IC chips while managing crosstalk through structured grouping and alternating bias line connections.
3Device complexity
If a single bias line is used to supply bias voltage to all conversion elements, then the device complexity is reduced, but uneven bias voltage distribution causes artifacts in radiation images
Solution Approach 1:
The patent segments the bias voltage distribution by providing multiple bias lines that supply bias voltage to different groups of conversion elements. Specifically, adjacent pixels are assigned to different bias lines in an alternating pattern, ensuring that pixels sharing signal lines receive bias voltage from different sources. This segmentation prevents uneven voltage distribution and reduces artifacts while maintaining manageable device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces artifacts in radiation images and lowers the cost of imaging apparatus components by optimizing the connection of pixels and bias lines, improving image quality and operational efficiency.
Implementation Method 1
Each of the pixels includes a thin-film transistor and a conversion element
Implementation Method 2
a two-dimensional matrix of pixels having photoelectric conversion elements and switch elements
Implementation Method 3
a first bias line for supplying a bias voltage from a first bias source to a plurality of the conversion elements arranged in the column direction, a second bias line for supplying a bias voltage from a second bias source different from the first bias source to the plurality of conversion elements arranged in the column direction
Data Source
AI summary
A difference in wiring capacitance between bias lines is reduced by equalizing, for pixels A connected to a signal line from a first direction and pixels B connected to the signal line from a second direction, the numbers of the pixels A and the pixels B where the pixels A and the pixels B are each connected to the corresponding bias line.