Split-Gate Memory Cell Self-Aligned Floating Gate
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Solution Overview
Problem
Conventional split-gate memory cells face challenges in further scaling down due to the non-self-aligned floating gate with shallow trench isolation and source line, hindering integration in high-density memory applications.
Innovation Solution
The floating gates are self-aligned with shallow trench insulators and source lines, with the source line formed by a polysilicon plug or through self-aligned source and shallow trench isolation etching, allowing for precise alignment of control and select gates, enabling efficient programming and erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional split-gate memory cell structure is used with non-self-aligned floating gate, then control gate and select gate can be formed, but memory cell size cannot be further reduced due to misalignment with shallow trench isolation and source line
Solution Approach 1:
The floating gate is formed first as a reference structure, then the shallow trench isolation and source line are formed in self-aligned manner relative to the floating gate. This preliminary formation of the floating gate enables subsequent structures to be precisely aligned to it, resolving the alignment precision issue while allowing further miniaturization of the memory cell
Solution Approach 2:
The floating gate serves as a self-aligning reference for the shallow trench isolation and source line formation. By using the floating gate itself as the alignment reference rather than requiring external alignment marks or processes, the manufacturing precision is improved without adding complex alignment steps, enabling further scaling of the memory cell size
Data Source
AI summary
Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.