ESD Inhibition Circuit for Integrated Circuits
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Solution Overview
Problem
Conventional integrated circuits are vulnerable to damage from electrostatic discharge (ESD) due to the inability of ESD protection circuits to enable protection immediately, leading to ESD current flowing through internal circuits and potentially causing false programming or damage, especially as semiconductor device sizes decrease and breakage voltages are reduced.
Innovation Solution
An integrated circuit design incorporating an ESD inhibition circuit that includes a capacitor bank, resistor, voltage selector, and switching transistor, which cooperates with the ESD protection circuit to prevent ESD current from reaching the internal circuit by isolating the pad and node through the switching transistor when an ESD zap is detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ESD protection circuit is designed to provide an ESD current path, then the internal circuit is protected from ESD damage, but the ESD protection circuit cannot be enabled immediately when ESD zap is received, causing partial ESD current to flow through the internal circuit
Solution Approach 1:
The ESD inhibition circuit is pre-configured with the switching transistor in a normally-on state before ESD event occurs. The capacitor bank is pre-charged through the resistor during normal operation. When ESD zap is detected, the pre-configured circuit immediately responds by turning off the switching transistor, eliminating the time delay associated with enabling protection circuits during ESD events.
Solution Approach 2:
The ESD inhibition circuit applies a counter-action by generating an inhibiting signal that turns off the switching transistor to block ESD current before it can reach the internal circuit. This preliminary anti-action prevents the harmful ESD current flow path from being established, complementing the ESD protection circuit's current diversion function.
2Productivity
If the semiconductor device size is decreased to increase operating speed and integration level, then the operating speed and integration level are improved, but the breakage voltage of the gate oxide layer and PN junction is reduced, making the circuit more vulnerable to ESD damage
Solution Approach 1:
The protection function is segmented into two independent circuits: the ESD protection circuit for diverting ESD current and the ESD inhibition circuit for blocking ESD current. This segmentation allows each circuit to be optimized for its specific function and work in parallel to provide comprehensive protection for the scaled-down internal circuit with reduced voltage tolerance.
Solution Approach 2:
The switching transistor serves as an intermediary element controlled by the ESD inhibition circuit to block the ESD current path to the internal circuit. The capacitor bank and resistor form an intermediary RC circuit that generates the inhibiting signal. This intermediary mechanism provides an additional layer of protection for the vulnerable scaled-down semiconductor devices.
3Reliability
If the ESD protection circuit is added to protect the internal circuit, then the internal circuit is protected from ESD current, but the device complexity increases due to the addition of ESD inhibition circuit components
Solution Approach 1:
The ESD inhibition circuit uses standard RC circuit components (resistor and capacitor bank) that can be integrated using the same fabrication processes as the rest of the circuit. The switching transistor utilizes the same transistor technology as the internal circuit. This multi-functionality approach allows the protection circuit to be implemented without requiring entirely new device types or fabrication processes, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively prevents ESD current from flowing into the internal circuit, thereby protecting it from damage by ensuring the switching transistor is turned off during ESD events, as demonstrated by the human body mode test results showing no internal circuit damage even under high ESD voltages.
Implementation Method 1
The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected between the first pad and a third node. The resistor is connected between the third node and the first node.
Implementation Method 2
An ESD inhibition circuit is provided. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. If the first input voltage is higher than the second input voltage, the first input voltage is selected by the voltage selector and transmitted to the output terminal of the voltage selector.
Data Source
AI summary
An integrated circuit is provided. An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected between the first pad and a third node. The resistor is connected between the third node and the first node. The two input terminals of the voltage selector are connected with the third node and a fourth node, respectively. An output terminal of the voltage selector is connected with a fifth node. A first terminal of the switching transistor is connected with the first pad. A second terminal of the switching transistor is connected with the second node. A gate terminal of the switching transistor is connected with the fifth node.