Vertical Transistor Strain Engineering for Carrier Mobility
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Solution Overview
Problem
Transistors with low carrier mobility result in reduced switching speed and decreased difference between 'on' and 'off' resistance, necessitating improvements in channel mobility.
Innovation Solution
The implementation of a vertical transistor design that incorporates a gate and inter-layer dielectric (ILD) to provide strain, with the gate configured to offer compressive strain for n-channels and tensile strain for p-channels, enhancing carrier mobility through specific material choices and deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor design is used, then manufacturing simplicity is maintained, but carrier mobility is insufficient
Solution Approach 1:
The patent transitions from planar transistor architecture to vertical transistor architecture, changing the current flow direction from lateral to vertical. This dimensional change enables better carrier mobility through the channel while maintaining manufacturability using adapted conventional processes.
Solution Approach 2:
The gate structure completely surrounds the channel in a nested configuration, with the gate wrapped around the channel region. This all-around gate structure provides enhanced electrostatic control and improves carrier mobility while maintaining a compact design that can be integrated into existing manufacturing flows.
2Speed
If carrier mobility is low, then device simplicity is maintained, but switching speed decreases
Solution Approach 1:
The patent modifies physical parameters including introducing strain through specific crystal orientations (e.g., <110> or <100> directions) and adjusting material composition in the channel region. These parameter changes enhance carrier mobility directly, enabling faster switching speeds while maintaining device reliability.
Solution Approach 2:
The transistor employs composite material structures with different materials in the channel, gate, and dielectric regions. Specific material combinations are selected to provide both high carrier mobility and fast switching characteristics, such as using strained silicon or III-V semiconductor materials in the channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively increases electron and hole mobility, thereby improving switching speed and resistance characteristics of transistors.
Implementation Method 1
The gate and the inter-layer dielectric are configured to provide strain substantially along an extending direction of the channel
Data Source
AI summary
A vertical transistor includes a source-channel-drain structure, a gate and a gate dielectric layer. The source-channel-drain structure includes a source, a drain over the source and a channel between the source and the drain. The gate surrounds a portion of the channel. The gate is configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the gate is configured to provide tensile strain substantially along the extending direction of the channel when the vertical transistor is a p-channel vertical transistor. In some embodiments, the vertical transistor further includes an ILD configured to provide tensile strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is a p-channel vertical transistor.