InGaO3ZnO Thin Film Transistor C-Axis Orientation
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Solution Overview
Problem
The high crystallization temperature of indium gallium zinc oxide requires complex and inefficient processes for thin film transistor manufacturing, affecting production efficiency and stability.
Innovation Solution
A method of forming an active layer with C-axis crystal orientation using indium gallium zinc oxide (InGaO3(ZnO)m, where m≧2, by depositing multiple layers under varying power and speed conditions, reducing the crystallization temperature and improving etching control, allowing for a back channel etching type structure that omits the need for an etch stop layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high crystallization temperature is used for indium gallium zinc oxide, then electron mobility is improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent changes the crystallization temperature parameter from conventional high temperatures to a reduced temperature range, achieving C-axis oriented crystal growth that maintains high electron mobility while simplifying the manufacturing process. This parameter change allows the oxide semiconductor layer to form the necessary crystal structure at lower temperatures, resolving the contradiction between mobility and process complexity
Solution Approach 2:
The patent uses indium gallium zinc oxide (InGaO3(ZnO)m) as a composite oxide semiconductor material with specific stoichiometric ratios, which enables reduced crystallization temperature while maintaining high electron mobility. The composite nature of this material allows optimization of both electrical properties and manufacturing characteristics
2Manufacturing precision
If conventional etch stop layer is used in oxide transistor, then etching control is achieved, but process complexity increases
Solution Approach 1:
The patent extracts and eliminates the etch stop layer from the conventional oxide transistor structure. By achieving C-axis oriented crystal growth in the oxide semiconductor layer itself, the patent obtains sufficient etching selectivity without requiring an additional etch stop layer, thereby reducing process complexity while maintaining manufacturing precision
Solution Approach 2:
The oxide semiconductor layer with C-axis orientation serves multiple functions simultaneously: it acts as the active channel layer providing high electron mobility and also provides the necessary etching selectivity that would otherwise require a separate etch stop layer. This multi-functionality reduces the overall process complexity
3Stability of the object's composition
If multiple deposition layers with varying parameters are used, then crystal orientation is improved, but deposition time increases
Solution Approach 1:
The patent segments the deposition process into multiple layers with different deposition conditions (power, speed, temperature). This segmentation allows each layer to contribute differently to the overall crystal structure, with the first layer providing initial nucleation and subsequent layers developing the C-axis orientation, achieving good crystal orientation while managing deposition time
4Productivity
If reduced crystallization temperature is used, then production efficiency is improved, but material properties may deteriorate
Solution Approach 1:
The patent changes the crystallization temperature parameter to a reduced range, which directly improves production efficiency by reducing manufacturing time and energy consumption. Simultaneously, the specific deposition parameters (power, speed, temperature combinations) are optimized to ensure that the reduced temperature still produces oxide semiconductor layers with the necessary C-axis orientation and high electron mobility, thus maintaining material properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the crystallization temperature, enhances production efficiency, improves the stability of the thin film transistor, and enables precise etching control, resulting in improved electron mobility and reduced production costs.
Implementation Method 1
a first indium gallium zinc oxide layer with C-axis orientation is deposited via a physical vapor deposition process under a first power and a first speed
Implementation Method 2
the active layer is formed in vacuum by using a Nd: YAG laser, wherein the laser has an output wavelength of 193-1064 nm, a repetition frequency larger than 1 Hz, and a pulse width less than 10 ns
Implementation Method 3
the first indium gallium zinc oxide layer and the second indium gallium zinc oxide layer are formed by a sputtering process in vacuum
Implementation Method 4
forming an active layer having characteristics of crystal orientation of C-axis on a substrate by using InGaO3(ZnO)m
Data Source
AI summary
A thin film transistor and a manufacturing method thereof, a display substrate and a display device are provided. The method of manufacturing the thin film transistor comprises forming an active layer (4) having characteristics of crystal orientation of C-axis on a substrate (1) by using indium gallium zinc oxide (InGaO3(ZnO)m), where m≧2. The active layer fabricated with InGaO3(ZnO)m has a good electron mobility, and the quality of the fabricated active layer is improved.