Oxide Semiconductor TFT Wiring Layout for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices using thin film transistors face challenges in reducing power consumption and achieving high reliability due to parasitic capacitance and contact resistance issues, particularly in oxide semiconductor layers.
Innovation Solution
A semiconductor device structure is developed with a gate electrode layer, oxide semiconductor layer, and source/drain electrode layers, where the source and drain electrode layers are thin and made of high oxygen affinity metals like titanium, and a wiring layer is formed with lower resistance materials, reducing parasitic capacitance and contact resistance through thermal treatment and dehydration/dehydrogenation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stacked-layer structure of gate electrode layer, gate insulating layer, and source/drain electrode layer is formed to improve electrical connection, then contact resistance is reduced, but parasitic capacitance increases leading to higher power consumption
Solution Approach 1:
The patent extracts the harmful stacked-layer structure between gate electrode and source/drain electrodes, removing the parasitic capacitance component while maintaining necessary electrical connections through alternative routing that avoids direct overlap, thereby reducing power consumption without sacrificing contact quality
Solution Approach 2:
The patent transitions from a vertical stacked-layer configuration to a planar arrangement where gate and source/drain electrodes are separated in the lateral dimension, eliminating parasitic capacitance through spatial separation while maintaining functional connectivity through optimized electrode geometry and routing
2Use of energy by moving object
If oxide semiconductor layer is used to reduce power consumption, then energy efficiency is improved, but contact resistance and reliability issues arise
Solution Approach 1:
The patent applies different material properties to different regions: using metals with high oxygen affinity (such as titanium) specifically at the source/drain electrode regions to reduce contact resistance, while maintaining the oxide semiconductor layer in the channel region for low power consumption, creating localized optimization of electrical properties
Solution Approach 2:
The patent employs composite material structures combining oxide semiconductor with metal layers having high oxygen affinity, where the metal oxide interface forms a low-resistance contact region that complements the insulating properties of the oxide semiconductor, achieving both low power consumption and high reliability
3Use of energy by moving object
If thin source and drain electrode layers are used to reduce parasitic capacitance, then power consumption is reduced, but contact resistance increases
Solution Approach 1:
The patent changes the material composition parameter of the source/drain electrodes by selecting metals with high oxygen affinity, which fundamentally alters the electrical properties at the metal-oxide interface, enabling thin electrode layers to achieve both low parasitic capacitance and low contact resistance through improved interfacial characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a semiconductor device with reduced power consumption and improved reliability by minimizing parasitic capacitance and contact resistance, enhancing the performance and longevity of thin film transistors in electronic devices.
Implementation Method 1
a gate insulating layer which covers the gate electrode layer, an oxide insulating layer which covers the source and drain electrode layers
Implementation Method 2
an oxide semiconductor layer which is in contact with the gate insulating layer
Implementation Method 3
dehydration/dehydrogenation processes
Implementation Method 4
dehydration/dehydrogenation processes
Implementation Method 5
a wiring layer over the oxide insulating layer, which is electrically connected to the source or drain electrode layer
Data Source
AI summary
It is an object to provide a semiconductor device with less power consumption as a semiconductor device including a thin film transistor using an oxide semiconductor layer. It is an object to provide a semiconductor device with high reliability as a semiconductor device including a thin film transistor using an oxide semiconductor layer. In the semiconductor device, a gate electrode layer (a gate wiring layer) intersects with a wiring layer which is electrically connected to a source electrode layer or a drain electrode layer with an insulating layer which covers the oxide semiconductor layer of the thin film transistor and a gate insulating layer interposed therebetween. Accordingly, the parasitic capacitance formed by a stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.