FinFET Metal Gate Work Function Tuning via Selective Etching
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Solution Overview
Problem
The semiconductor industry faces challenges in efficiently forming work function layers in FinFET devices due to difficulties in precise etching processes, which can result in damage to gate dielectric layers and loss of critical dimensions, especially in complex gate trench structures like Y-shaped or tri-gate configurations.
Innovation Solution
A two-step wet etching process is employed to selectively remove capping and work function layers, using specific chemical mixtures to avoid attacking underlying layers, combined with a method that forms metal gates with different work function layers to tune threshold voltages, allowing for precise control and flexibility in FinFET device fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-step etching process is used to remove capping and work function layers, then the manufacturing process is simpler and faster, but it causes damage to gate dielectric layers and loss of critical dimensions
Solution Approach 1:
The etching process is divided into two distinct steps: a first etching step that selectively removes the capping layer, and a second etching step that selectively removes the work function layer. This segmentation allows each step to be optimized for its specific target layer, preventing damage to underlying gate dielectric layers while maintaining manufacturing efficiency.
2Productivity
If aggressive etching chemicals are used to efficiently remove work function layers, then the etching speed increases, but it attacks and damages the underlying gate dielectric layer
Solution Approach 1:
The first etching step acts as an intermediary process that selectively removes the capping layer to expose the work function layer, while the second etching step then selectively removes the work function layer. This two-step intermediary approach allows aggressive chemicals to be used in the second step without damaging the gate dielectric, as the work function layer protects it during that step.
Solution Approach 2:
The etching process uses different chemical parameters for each step: the first etching step uses chemicals selective to the capping layer, while the second etching step uses chemicals selective to the work function layer. This parameter change allows efficient removal of each layer without attacking the underlying gate dielectric structure.
3Adaptability or versatility
If metal gates with different work function layers are formed to tune threshold voltages, then the device functionality and performance are improved, but the fabrication process complexity increases
Solution Approach 1:
Different work function layers are formed in different regions of the semiconductor device to create local variations in threshold voltage. This allows NMOS and PMOS transistors to have optimized electrical characteristics tailored to their specific requirements, improving overall device performance while using a systematic fabrication approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise and selective etching, reducing damage to gate dielectric layers and maintaining critical dimensions, while allowing for flexible tuning of threshold voltages, thereby improving the performance and functionality of FinFET devices.
Implementation Method 1
selectively removing the capping layer in the first recess to expose the N-type work function layer in the first recess using a first wet etch process; and selectively removing the N-type work function layer in the first recess to expose the gate dielectric layer in the first recess using a second wet etch process different from the first wet etch process
Data Source
AI summary
A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin protruding above a substrate, where the first dummy gate structure and the second dummy gate structure are surrounded by a dielectric layer; and replacing the first dummy gate structure and the second dummy gate structure with a first metal gate and a second metal gate, respectively, where the replacing includes: removing the first and the second dummy gate structures to form a first recess and a second recess in the dielectric layer, respectively; forming a gate dielectric layer in the first recess and in the second recess; forming an N-type work function layer and a capping layer successively over the gate dielectric layer in the second recess but not in the first recess; and filling the first recess and the second recess with an electrically conductive material.