Vertical TFT with Perforated Gate Electrodes for Fast Switching

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional thin film transistors (TFTs) with a planar Source-Drain structure have limited transistor mobility and controllable drain current due to their lateral active channel design, resulting in slow switching times and high operational voltage, which hinders their application in flexible and wearable devices.

Innovation Solution

A vertical-structure TFT with a gate electrode structure that allows electron flow, featuring a semiconductor layer between vertically positioned source and drain electrodes, and embedded comb-like or perforated gate electrodes to enhance current flow and reduce switching time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a lateral active channel design is used in conventional TFTs, then the device structure is simple and easy to manufacture, but the transistor mobility is limited and switching times are slow

Engineering Contradiction:
Improveease of manufactureVSAvoidswitching times
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The patent transitions from a conventional lateral channel design to a vertical channel architecture, changing the dimension of current flow from horizontal to vertical. This dimensional change enables shorter channel lengths while maintaining ease of manufacturing through standard thin film deposition and etching processes, thereby achieving faster switching times without sacrificing manufacturability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If a lateral active channel design is used in conventional TFTs, then the device structure is simple, but the controllable drain current is limited and operational voltage is high

Engineering Contradiction:
Improvedevice structureVSAvoidoperational voltage
Core Design Contradiction:
Device complexityVSPower

Solution Approach 1:

By implementing a vertical channel structure with the gate electrode positioned at the bottom, the patent achieves better gate control over the channel. This vertical configuration allows for shorter effective channel lengths and improved electrostatic control, enabling lower operational voltages and higher controllable drain current while maintaining relatively simple device structure through standard fabrication processes

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If the channel length is increased to improve current control, then the gate control improves, but the switching time increases and speed decreases

Engineering Contradiction:
Improvegate controlVSAvoidswitching time
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The vertical channel architecture enables independent optimization of channel length and gate control. The gate electrode positioned at the bottom provides excellent electrostatic control over the vertical channel, while the channel length can be kept short to maintain fast switching speeds. This vertical configuration decouples the trade-off between gate control and switching speed that plagues lateral channel designs

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20220052172A1Vertical thin film transistor with perforated or comb-gate electrode configuration and fabrication methods for same
Publication Date: 2022.02.17 SOLSONA ENTERPRISE LLC
  • US20220052172A1 patent drawing
  • US20220052172A1 patent drawing
  • US20220052172A1 patent drawing

AI summary

The present invention provides a vertical-type thin film transistor (TFT) and methods of fabricating vertical TFTs. The vertical TFT may comprise a source electrode and a drain electrode, the drain electrode and the source electrode being positioned on vertically separated planes. A semiconductor layer may be arranged in between the source electrode and the drain electrode. At least one gate electrode may be embedded in the semiconductor layer. At least one of the source electrode and the drain electrode comprise patterned electrodes. One or all of the gate electrodes, the source electrode and the drain electrode may be patterned electrodes. The patterned electrodes may comprise one or more of fingers or combs, micro perforations, a mesh structure, or a lattice structure. Back side exposed fabrication techniques may be used to fabricate various of the vertical TFT embodiments.