Buried Gate BCAT Devices with Planar Bit Lines
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Solution Overview
Problem
Conventional buried channel array transistor (BCAT) devices have high loading capacitance and tall heights due to elevated bit lines, which degrade device characteristics and increase fabrication complexity.
Innovation Solution
The BCAT devices are designed with bit lines directly connected to the semiconductor substrate and active regions, reducing height and loading capacitance by having bit lines extend along the same plane as the substrate, and using a simplified fabrication process with fewer photoresist steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are arranged above the substrate in conventional BCAT devices, then the bit lines can be positioned to connect active regions, but the loading capacitance increases and the device height increases
Solution Approach 1:
The bit lines are repositioned from a vertical arrangement above the substrate to a horizontal arrangement extending along the same plane as the substrate surface. This dimensional change allows direct connection to active regions without vertical stacking, reducing both loading capacitance and device height while maintaining electrical connectivity.
2Manufacturing precision
If conventional fabrication processes are used for BCAT devices, then complete device structure can be formed, but the number of fabrication steps increases
Solution Approach 1:
The fabrication process merges previously separate steps into a single integrated process. Specifically, the formation of bit lines and their connection to active regions is combined into one fabrication step, eliminating the need for separate conductive plug formation and reducing the total number of photoresist steps required.
Data Source
AI summary
A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, a plurality of buried gate electrodes extending below an upper surface of the semiconductor device, and a plurality of bit lines extending along a first direction over the semiconductor substrate, wherein the plurality of bit lines are connected to corresponding ones of the active regions of the semiconductor substrate, and at least a portion of the bit lines extend along a same and/or substantially same plane as an upper surface of the corresponding active region to which it is connected.


