Imaging Device Back Gate Transistor High Speed Readout
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Solution Overview
Problem
Current imaging devices face challenges in achieving high-speed operation, long signal holding periods, low power consumption, high definition, high sensitivity, wide dynamic range, high resolution, and cost-effectiveness while maintaining reliability.
Innovation Solution
The imaging device incorporates a pixel structure with multiple transistors, including back gate electrodes, using oxide semiconductors and a selenium-based photoelectric conversion film, where the back gate electrodes are connected to shared wirings to control potential and enhance transistor performance, allowing for high-speed and low-power operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels in an imaging device is increased to achieve high resolution, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The imaging device is divided into multiple pixels, each with its own photodiode and transistor circuit. This segmentation allows independent operation of each pixel unit, enabling high resolution through increased pixel count while managing overall device complexity through modular design
Solution Approach 2:
The transistor circuit configuration is made universal across all pixels, with each pixel containing the same functional elements (photodiode, first transistor, second transistor, third transistor, fourth transistor). This multi-functionality allows the same circuit design to be replicated across numerous pixels, achieving high resolution without proportionally increasing design complexity
2Measurement precision
If the number of pixels is increased to achieve high resolution, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The imaging device operates in periodic cycles of signal accumulation and readout. During the accumulation phase, pixel circuits hold signals without active readout, minimizing power consumption. The readout operation occurs periodically, allowing high resolution across many pixels while consuming power only during necessary operations
Solution Approach 2:
Each pixel circuit is self-contained with its own signal holding capability through the transistor configuration. The pixel circuits can maintain their signals independently without requiring continuous power supply or active management from external circuits, reducing overall power consumption while maintaining high resolution across multiple pixels
3Productivity
If high-speed operation is required, then productivity is improved, but signal holding period may be reduced
Solution Approach 1:
The transistor circuits provide dynamic control over signal holding. The transistors can switch between holding signals and rapid readout modes, allowing the system to adapt between long signal holding periods for integration and fast readout for high-speed operation, resolving the contradiction between speed and holding duration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed operation, extended signal holding periods, low power consumption, high sensitivity, and a wide dynamic range while maintaining high resolution and reliability, and is cost-effective.
Implementation Method 1
a plurality of pixels each including a photodiode
Implementation Method 2
The back gate electrode of the first transistor is electrically connected to a wiring that can switch and supply a potential higher than a source potential of the first transistor and a potential lower than the source potential of the first transistor
Data Source
AI summary
To provide an imaging device capable of high-speed reading. The imaging device includes a photodiode, a first transistor, a second transistor, a third transistor, and a fourth transistor. The back gate electrode of the first transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the first transistor and a potential lower than the source potential of the first transistor. The back gate electrode of the second transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the second transistor. The back gate electrode of the third transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the third transistor and a potential lower than the source potential of the third transistor.