Multigate Air-Gap Spacer and Backside Rail Contact for RC Scaling
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Solution Overview
Problem
As integrated circuit (IC) devices scale down, challenges arise in achieving desired gate density and performance due to increased resistance in metal interconnect lines and higher capacitance in dielectric features, which affect device performance and manufacturing complexity.
Innovation Solution
The introduction of an air gap inner spacer and backside metallization routing, allowing for reduced capacitance and improved performance by using a dielectric constant near 1 for the air gap and increasing the width of metallization lines on the backside, thereby lowering resistance and enhancing circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC dimensions are reduced to improve production efficiency and lower costs, then productivity increases, but device performance deteriorates due to increased resistance and higher capacitance
Solution Approach 1:
The patent applies local quality by introducing air gap spacers at specific locations between the gate structure and source/drain regions, rather than uniformly modifying the entire device. The air gap dielectric (with dielectric constant near 1) is locally positioned to reduce capacitance in critical areas, while maintaining conventional dielectric materials in other regions. This localized modification addresses the capacitance issue without requiring complete redesign of the scaled device architecture.
Solution Approach 2:
The patent changes the dielectric parameter (dielectric constant) by introducing air gap spacers with dielectric constant near 1, replacing conventional dielectric materials with higher dielectric constants. This parameter change directly reduces the capacitance between gate and source/drain regions, counteracting the performance degradation caused by device scaling while maintaining the scaled dimensions for high productivity.
2Quantity of substance
If device dimensions are scaled down to increase gate density, then gate density improves, but resistance increases due to smaller conductive features
Solution Approach 1:
The patent addresses the resistance issue by introducing air gap spacers that extend vertically between the gate structure and source/drain regions, utilizing the vertical dimension to reduce capacitance and improve electrical characteristics. This dimensional approach allows the device to maintain scaled horizontal dimensions for high gate density while using vertical spacing to mitigate resistance and capacitance effects.
3Ease of manufacture
If conventional dielectric materials are used in scaled devices, then manufacturing simplicity is maintained, but capacitance increases and performance deteriorates
Solution Approach 1:
The patent maintains manufacturing simplicity by using conventional dielectric materials in most regions while introducing air gap spacers with near-zero dielectric constant in specific critical regions. This local substitution of dielectric material allows the majority of the device to be manufactured using existing processes, while the air gap regions provide the necessary capacitance reduction for improved performance.
Solution Approach 2:
The patent changes the dielectric parameter from conventional values (typically 3-10) to near 1 for air gap spacers, creating a stark parameter contrast that significantly reduces capacitance. This parameter change is applied selectively in spacer regions while maintaining conventional dielectric parameters in other device regions, balancing performance improvement with manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces capacitance and improves speed and performance of multigate devices by utilizing air gaps and increased backside metallization line widths, addressing the scaling challenges in IC manufacturing while maintaining gate control and integrating with conventional processes.
Implementation Method 1
reduced capacitance and improved performance by using a dielectric constant near 1 for the air gap
Data Source
AI summary
Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.