Stacked MOSFET Channel Layout With Buffer Width Transition
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in reliability and electric characteristics.
Innovation Solution
A semiconductor device design featuring vertically stacked and spaced semiconductor patterns with varying channel widths, including a buffer channel pattern, and a gate electrode structure that extends in a specific direction, along with metal-semiconductor compound layers and interconnection lines, to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for small pattern size, then device size is reduced, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel patterns. Multiple semiconductor patterns are stacked in the vertical direction to form channel patterns, enabling the device to maintain adequate channel area for reliable operation while occupying less lateral space. This dimensional transition resolves the contradiction by providing sufficient active area for performance while achieving compact footprint.
Solution Approach 2:
The channel pattern is segmented into multiple discrete semiconductor patterns stacked vertically, with gate electrodes wrapping around each pattern. This segmentation allows independent control and optimization of each stacked channel segment, maintaining operational reliability through proper electrical isolation and controlled conductivity paths while achieving high density through vertical stacking.
2Reliability
If channel pattern width is varied to improve device performance, then electric characteristics are enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent implements varying channel widths at different lateral positions through the buffer channel pattern, which has a width intermediate between the first and second channel patterns. This local variation in dimensions allows optimization of electrical characteristics in specific regions while maintaining a systematic, repeatable fabrication process. The buffer pattern serves as a transition zone that manages electrical properties locally without requiring complex global restructuring.
Data Source
AI summary
A semiconductor device may include an active region on a substrate, channel patterns on the active region, and gate electrodes on the channel patterns, respectively, and extending in a first direction. The channel patterns may include a first subset of the channel patterns, each of which has a first width, and a second subset of the channel patterns, each of which has a second width. The first and second subsets may be adjacent to each other in a second direction. The channel patterns may further include a buffer channel pattern between the first subset and the second subset. The buffer channel pattern may include a connection side surface extending in the first direction, and the connection side surface may be configured such that a width of the buffer channel pattern changes from the first width to the second width when moving from the first subset to the second subset.