Twin Memory Cells With Shared Vertical Control Gate
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Solution Overview
Problem
The existing memory array and cell structure is complex for word-erasable applications, requiring division of control gate lines and additional voltage switches, and involves applying negative voltages to twin memory cells during read operations, which complicates the control units and increases complexity.
Innovation Solution
The proposed solution involves a memory cell structure with dual floating-gate transistors and a shared vertical control gate, allowing for independent erasing and reading of memory cells without applying negative voltages to twin cells, using a reading circuit that allocates the same line address to control gate lines and selects the appropriate control gate line based on the column address, and includes an additional bit line for each memory cell to enable reading without negative voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the memory array structure uses twin memory cells with shared vertical select gates, then the footprint is reduced, but the control complexity increases for word-erasable applications
Solution Approach 1:
The control gate line is divided into multiple segments, with each segment connected to a specific memory cell through a selection mechanism. This segmentation allows independent control of individual memory cells while using the shared vertical select gate structure, thereby reducing control complexity for word-erasable applications while maintaining the compact footprint.
Solution Approach 2:
The patent introduces a new dimension of control by using vertically stacked control gate lines at different heights. This three-dimensional arrangement allows selective activation of specific memory cells along the vertical axis, enabling word-erasable functionality without increasing the planar footprint and without requiring complex lateral control wiring.
2Measurement precision
If negative voltage is applied to twin memory cells during read operations, then the selected memory cell can be read, but the control unit complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring the control gate line voltages before the read operation. The control gate line is prepared with appropriate voltage levels in advance, and the selection of the specific memory cell is made through the vertical select gate mechanism, eliminating the need for complex real-time voltage switching during the read operation.
Solution Approach 2:
The vertical select gate acts as an intermediary element between the control logic and the memory cell. It mediates the selection process by responding to control signals and enabling or disabling current flow to the selected cell, thereby simplifying the control unit's task of managing negative voltage application during read operations.
3Adaptability or versatility
If control gate lines are divided for word-erasable applications, then individual word erasing is enabled, but the decoder complexity increases
Solution Approach 1:
The control gate line is segmented into multiple sections, each corresponding to a specific word in the memory array. This segmentation enables independent erasing of individual words by activating only the relevant segment, providing word-erasable capability while keeping the decoder logic simple through the use of the shared vertical select gate structure.
Solution Approach 2:
The shared vertical select gate structure serves multiple functions: it acts as the select gate for twin memory cells during read/write operations and simultaneously serves as the control mechanism for word-erasable functionality. This multi-functionality eliminates the need for separate control mechanisms, thereby reducing decoder complexity while maintaining adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure simplifies the control units, allows for individual erasing of memory cells, reduces erasing stress on connected cells, and enables reading without negative voltages, improving the efficiency and complexity of word-erasable memory arrays.
Implementation Method 1
Such memory cells are channel-erased or programmed, i.e., by putting the substrate to a positive erase voltage or negative programming voltage causing electric charges to be extracted from their floating gates or electric charges to be injected into their floating gates, by Fowler Nordheim effect.
Data Source
AI summary
The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell.