Multi-Vt Gate-All-Around Transistors via Dipole Diffusion

The patent implements different gate dielectric thicknesses in different regions of the semiconductor device. Specifically, first gate dielectric layers are formed with a first thickness in first regions, while second gate dielectric layers are formed with a second thickness in second regions. This local differentiation allows high voltage devices to have thicker dielectrics for adequate spacing while low voltage logic devices can have thinner dielectrics for higher density, thereby resolving the contradiction between device density and device-device spacing for higher voltage operation.

The patent applies different gate dielectric thicknesses to different functional regions. High voltage devices (such as input/output circuits) receive thicker gate dielectric layers that provide the necessary breakdown voltage and reliability, while logic devices receive thinner gate dielectric layers that enable continued scaling and higher device density. This localized approach allows the system to achieve both high voltage operation capability and continued device scaling.

The patent achieves multi-threshold voltage capability by changing the physical parameters of the gate structure. Specifically, it varies the thickness of gate dielectric layers and work function metal layers across different regions. By controlling these dimensional parameters during deposition, the patent creates devices with different threshold voltages without requiring additional patterning steps or complex manufacturing processes, thus obtaining multi-Vt capability while minimizing manufacturing complexity.