Vertical Flash-Cell Neuromorphic Array for Analog Weight Computing
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Solution Overview
Problem
Current neural network implementations, particularly in software or digital CMOS processors, are inefficient due to complex digital computations required for artificial neurons, involving numerous floating-point multiplications and additions.
Innovation Solution
A neuromorphic device is developed for analog computation, featuring a vertical stack of flash-like cells with a common control gate and individually contacted source-drain regions, enabling efficient layout resource use and non-volatile programming, allowing for fast evaluation and programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital CMOS processors are used to implement neural networks, then computational flexibility is maintained, but device complexity and processing time increase significantly
Solution Approach 1:
The patent replaces digital CMOS computational systems with a neuromorphic device that uses analog memory (flash-like cells) to perform computations. This substitution eliminates the need for complex digital circuits that perform floating-point multiplications and additions, instead using the physical properties of memory cells to directly compute neural network operations, thereby reducing device complexity while maintaining or improving processing speed
Solution Approach 2:
The patent changes the operational parameters from digital voltage levels representing binary states to analog charge states in floating gates that represent continuous weight values. This parameter change allows the system to perform computations in the analog domain, reducing the number of computational steps and circuit complexity required while achieving faster processing times
2Area of stationary object
If vertical stacking of flash-like cells is implemented, then layout resource efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar (2D) arrangement of memory cells to a vertical (3D) stacked configuration. By stacking multiple flash-like cells vertically with shared control gates, the device achieves higher density and more efficient layout resource utilization. This dimensional change allows computations to be performed with fewer devices while reducing the overall layout area, though it does require precise alignment during fabrication
Data Source
AI summary
A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.