Bilayer Isolation Layers for Stacked Transistor S/D Epitaxy
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Solution Overview
Problem
The fabrication of complementary field-effect transistors (CFETs) faces challenges in proper isolation of source/drain epitaxial structures between vertically stacked transistors, which affects transistor density and performance, particularly in gate-all-around (GAA) FETs and combinations with finFETs.
Innovation Solution
The implementation of a bilayer isolation structure comprising an oxygen-free bottom layer and a low-k top layer, deposited and etched to ensure adequate protection and minimize parasitic capacitance, with specific thicknesses and materials like silicon nitride and silicon oxide, to effectively isolate S/D epitaxial structures in CFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer isolation structure is used, then the fabrication process is simpler, but the protection against oxidation and control of parasitic capacitance are insufficient
Solution Approach 1:
The isolation structure is divided into two distinct layers: a first dielectric layer (oxygen-free, such as silicon nitride) and a second dielectric layer (oxygen-containing, such as silicon oxide). Each layer serves a specific function—the first layer provides oxidation protection while the second layer controls parasitic capacitance. This segmentation allows independent optimization of each layer's properties to address both protection and capacitance control requirements simultaneously.
Solution Approach 2:
The isolation structure employs a composite bilayer configuration combining two different dielectric materials with complementary properties. The oxygen-free dielectric material (first layer) and oxygen-containing dielectric material (second layer) are deposited in sequence to create a composite structure that leverages the advantages of both materials—oxidation resistance from the first layer and low parasitic capacitance from the second layer.
2Reliability
If the isolation layer thickness is increased to improve isolation, then oxidation protection is enhanced, but parasitic capacitance increases
Solution Approach 1:
Different regions of the isolation structure have different compositions and functions. The first dielectric layer (oxygen-free) is optimized for oxidation protection with appropriate thickness, while the second dielectric layer (oxygen-containing) is optimized for parasitic capacitance control. By assigning different local qualities (oxygen-free vs. oxygen-containing) to different layers, the structure achieves both protection and low capacitance without requiring uniform thickness increases throughout the entire isolation layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the isolation between vertically stacked transistors, improving transistor density and reducing parasitic capacitance, thereby increasing the efficiency and performance of CFETs by maintaining a balance between oxidation protection and capacitance characteristics.
Implementation Method 1
depositing an oxygen-free dielectric on the first S/D epitaxial structures
Implementation Method 2
oxidizing the deposited oxygen-free dielectric
Implementation Method 3
etching the oxidized oxygen-free dielectric
Implementation Method 4
depositing an oxygen-free dielectric on the first S/D epitaxial structures
Implementation Method 5
depositing an oxygen-containing dielectric on the first layer
Data Source
AI summary
The present disclosure is directed to a method for the fabrication of isolation structures between source/drain (S/D)) epitaxial structures of stacked transistor structures. The method includes depositing an oxygen-free dielectric material in an opening over a first epitaxial structure, where the oxygen-free dielectric material covers top surfaces of the first epitaxial structure and sidewall surfaces of the opening. The method also includes exposing the oxygen-free dielectric material to an oxidizing process to oxidize the oxygen-free dielectric material so that the oxidizing process does not oxidize a portion of the oxygen-free dielectric material on the first epitaxial structure. Further, etching the oxidized oxygen-free dielectric material and forming a second epitaxial layer on the oxygen-free dielectric material not removed by the etching to substantially the opening.