Metal Gate Structure With Gate-Cut Contact for Channel Isolation
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Solution Overview
Problem
Conventional methods for forming metal gate structures in semiconductor devices face challenges such as insufficient line-end process window and prolonged etch times for channel isolation trenches, leading to reduced device performance and production yield.
Innovation Solution
The method involves forming channel isolation features before metal gates and gate-cut features after metal gate formation, which simplifies the process, enlarges the process window, and improves yield by avoiding complex etching through active regions of GAA FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channel isolation trenches are formed after metal gate structures are formed, then channel isolation can be achieved, but etch time is prolonged and device performance is damaged
Solution Approach 1:
The channel isolation trench is formed before the metal gate structure is formed. This preliminary action allows the trench to be etched through the semiconductor substrate while the gate dielectric layer and gate electrode are still present, significantly reducing the etch time required and preventing damage to the gate structure that would occur if the trench were formed afterward.
Solution Approach 2:
The formation process is segmented into distinct stages: first forming the channel isolation trench through the substrate, then forming the gate dielectric layer and metal gate structure separately. This segmentation allows each component to be optimized independently and avoids the need for prolonged etching through already-formed gate structures.
2Manufacturing precision
If gate replacement is used to form metal gate structures, then metal gates can be formed, but the line-end process window is insufficient due to gate dielectric layer on sidewalls
Solution Approach 1:
The gate dielectric layer is selectively removed from the sidewalls at the line-end regions through targeted etching processes. This extraction of the dielectric layer from specific locations creates adequate space for metal gate electrode formation while maintaining the gate dielectric in other regions where it is needed for device operation.
Solution Approach 2:
The gate structure is given different properties in different regions: in the line-end regions, the sidewall dielectric is removed to facilitate metal gate formation, while in the active channel regions, the gate dielectric is maintained to ensure proper device operation. This local differentiation resolves the contradiction between process window and structural complexity.
Data Source
AI summary
A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.