Undulating Via Interconnect Structure for Lower Contact Resistance
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Solution Overview
Problem
As integrated circuit technologies progress towards smaller technology nodes, the interconnect structures between gate structures and source/drain features in semiconductor devices face challenges such as increased resistance due to long conductive paths and inadequate contact areas, leading to high contact and sheet resistance, which affects device performance.
Innovation Solution
The implementation of undulating-shaped via structures that provide a non-linear conductive path between device-level contact structures and metallization layers, increasing the contact area and reducing the path length, thereby decreasing resistance and potentially mitigating leakage by defining concave portions to insulate from adjacent features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional linear via structures are used, then the fabrication process is simple, but the contact area is insufficient and the conductive path length is long, resulting in high contact and sheet resistance
Solution Approach 1:
The patent applies curvature by transforming the conventional linear via structure into an undulating-shaped via structure with sinusoidal or triangular wave patterns. This curvature increases the contact area between the via and adjacent conductive features (such as source/drain regions and metal lines) while maintaining a compact footprint. The undulating shape provides multiple contact points along the via sidewalls, thereby reducing contact and sheet resistance without significantly complicating the fabrication process
Solution Approach 2:
The patent transitions from a two-dimensional linear via structure to a three-dimensional undulating structure by introducing vertical undulations along the via sidewalls. This dimensional change increases the effective contact area and provides additional conductive pathways through the via structure, reducing resistance while maintaining the same planar footprint. The undulating shape creates multiple interfaces with adjacent conductive features, effectively utilizing the vertical dimension to improve electrical connectivity
2Reliability
If the via structure is made larger to increase contact area, then resistance decreases, but the spacing between gate structures and source/drain features becomes insufficient
Solution Approach 1:
The undulating shape of the via structure increases the effective contact area along the via sidewalls without increasing the planar footprint. The sinusoidal or triangular wave patterns create multiple contact points with adjacent conductive features, reducing sheet resistance while maintaining adequate spacing between gate structures and source/drain features. The curvature allows the via to maximize its interface area within the available vertical space
Solution Approach 2:
The patent utilizes the vertical dimension by creating undulations along the via sidewalls, which increases the contact area without expanding the horizontal footprint. This dimensional approach allows the via structure to achieve lower resistance while maintaining the required spacing between adjacent features in the planar direction, effectively decoupling resistance reduction from lateral dimension increases
Data Source
AI summary
A method and device according to the present disclosure includes a substrate that has a first transistor terminal such as a source feature and a second transistor terminal such as another source feature. Contact structures are formed on each source/drain feature. After forming the contact structures, a via opening is formed in dielectric materials above the contact structures, which is filled to form a non-linear via that extends from the contact on the first source feature to the contact on the second source feature. The non-linear via may include an outline in a top view of an undulating-shape having convex and/or concave portions.