Polysilicon Layer Co-Integration for Flash Memory and Bipolar Transistors
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Solution Overview
Problem
The complexity and cost of manufacturing silicon wafers that integrate multiple devices, such as flash memory and bipolar transistors, are increased due to the need for multiple processing steps and masks, making it difficult to achieve efficient co-integration of different components on the same chip.
Innovation Solution
A method that uses a single polysilicon layer deposition and a single ion implant step to form both the flash memory region and bipolar transistors, reducing the number of processing steps and masks required, and allowing for the co-integration of vertical NPN and PNP bipolar transistors with flash memory devices on the same silicon wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple processing steps and masks are used to integrate flash memory and bipolar transistors on the same silicon wafer, then device functionality is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the processing steps for flash memory and bipolar transistors by using a single polysilicon layer deposition to form both the control gate of the flash memory device and the base contact of the bipolar transistor. This combining of previously separate processing sequences into a unified flow reduces the total number of masks and processing steps required, directly addressing the contradiction between integration capability and manufacturing complexity
Solution Approach 2:
The polysilicon layer serves multiple functions simultaneously: it forms the control gate electrode for the flash memory device and the base contact for the bipolar transistor. This multi-functional use of a single material layer eliminates the need for separate deposition steps for each device type, reducing process complexity while maintaining the ability to fabricate different device structures on the same wafer
2Reliability
If multiple processing steps are used to form flash memory and bipolar transistors separately, then device performance is ensured, but the number of processing steps increases
Solution Approach 1:
The patent combines the polysilicon deposition steps for flash memory control gate and bipolar transistor base contact into a single processing step. This merging maintains device performance by ensuring both structures receive the same high-quality polysilicon layer with controlled thickness and doping, while simultaneously improving manufacturing efficiency by reducing the total number of processing steps and increasing throughput
3Ease of manufacture
If a single polysilicon layer is used for both flash memory and bipolar transistor, then process simplification is achieved, but device structure requirements must be satisfied
Solution Approach 1:
The patent applies local quality by using the same polysilicon layer deposited with uniform properties throughout the wafer, but then applying different subsequent processing steps to different regions. The flash memory regions receive processing to form tunnel oxides and charge trapping layers, while bipolar transistor regions receive processing to form emitter and collector structures. This allows the single polysilicon layer to satisfy different device structure requirements through spatially differentiated subsequent processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces costs and expertise needed, and enables the efficient production of silicon wafers with multiple devices, such as vertical NPN and PNP bipolar transistors, and flash memory regions, while minimizing the number of epitaxial steps and masks required.
Implementation Method 1
a step of depositing a single polysilicon layer common to both the flash memory region and the bipolar transistor
Implementation Method 2
a single implant step common to both the flash memory region and the bipolar transistor
Data Source
AI summary
Methods and systems for processing a silicon wafer are disclosed. A method includes providing a flash memory region in the silicon wafer and providing a bipolar transistor with a polysilicon external base in the silicon wafer. The flash memory region and the bipolar transistor are formed by depositing a single polysilicon layer common to both the flash memory region and the bipolar transistor.