Convex Metal Gate Profile to Prevent Via-to-Gate Leakage

Solution Overview

Problem

Metal gates and source/drain contacts in integrated circuits suffer from bridge leakage due to variations in critical dimension or misalignment of contact vias during processing, leading to performance degradation.

Innovation Solution

The implementation of a semiconductor device structure with gate electrode layers having a convex top surface profile, achieved through a metal gate etching back process that forms micro-trenches with a smooth rounded surface, preventing unwanted connections with misaligned contact vias and enhancing manufacturing precision.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional flat gate electrode layers are used, then manufacturing is simpler, but contact via misalignment causes bridge leakage and device failure

Engineering Contradiction:
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate electrode layer is designed with a convex curved surface instead of a flat surface. This curvature creates a geometric barrier that prevents contact vias from bridging to the gate electrode even when misalignment occurs, thereby improving reliability without requiring complex additional structures

Inventive Principle:
Principle #14Spheroidality (Curvature)

Solution Approach 2:

The solution transitions from a two-dimensional flat gate electrode to a three-dimensional convex structure. By adding the vertical dimension of curvature, the design creates a protective barrier that addresses misalignment issues in the horizontal plane through geometric configuration in the vertical dimension

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If contact vias are positioned closer to gate electrode, then device density increases, but misalignment causes increased leakage

Engineering Contradiction:
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The convex curvature of the gate electrode layer creates a gradual geometric transition that acts as a natural barrier. This allows contact vias to be positioned closer to the gate electrode for higher density while the curved surface prevents sudden bridging, thereby reducing leakage without sacrificing density

Inventive Principle:
Principle #14Spheroidality (Curvature)

3Reliability

If strict contact via alignment is enforced, then bridge leakage is prevented, but manufacturing complexity and cost increase

Engineering Contradiction:
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

Instead of requiring precise alignment through complex processing, the convex curved surface provides inherent geometric protection. This approach relaxes alignment requirements while maintaining reliability, as the curvature naturally prevents bridging even with typical manufacturing variations

Inventive Principle:
Principle #14Spheroidality (Curvature)

Solution Approach 2:

The design accepts that misalignment will occur during manufacturing but converts this potential defect into a non-issue by using the convex geometry to tolerate misalignment. The curvature transforms the harmful effect of misalignment into an acceptable variation, simplifying manufacturing while maintaining device performance

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS20230335610A1Semiconductor device structure and methods of forming the same
Publication Date: 2023.10.19
  • US20230335610A1 patent drawing
  • US20230335610A1 patent drawing
  • US20230335610A1 patent drawing

AI summary

Embodiments of the present disclosure relates to a semiconductor device structure, including a first gate dielectric layer having a top surface and a corner surface, wherein a highest point of the top surface of the first gate dielectric layer is at a first elevation. The semiconductor device structure includes a first gate electrode layer having a top surface, wherein a highest point of the top surface of the first gate electrode layer is at a second elevation higher than the first elevation. The semiconductor device structure includes a first dielectric cap layer in contact with the top surface and the corner surface of the first gate dielectric layer. The first dielectric cap layer is also in contact with the top surface of the first gate electrode layer. The semiconductor device structure includes a first gate spacer in contact with the first dielectric cap layer and the first gate dielectric layer.