Trench Semiconductor Device Integrating 2D Material Layer
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Solution Overview
Problem
Current semiconductor devices face limitations in integrating two-dimensional material layers effectively into their structure, which can impact the performance and efficiency of transistors and other circuit components.
Innovation Solution
A trench-type semiconductor device is developed, featuring a substrate with a dielectric layer, a hard mask layer, and a two-dimensional material layer, along with source/drain electrode layers and a gate dielectric layer, allowing for the integration of 2D materials over the trench structure, enhancing transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two-dimensional material layers are integrated into semiconductor device structure, then device performance and efficiency are improved, but manufacturing complexity increases
Solution Approach 1:
The device structure is segmented into distinct functional regions including a trench structure with source/drain electrodes, gate electrode, and two-dimensional material channel region. This segmentation allows each component to be optimized independently while maintaining overall device performance
Solution Approach 2:
The patent transitions from conventional two-dimensional planar transistor structures to a three-dimensional trench-type structure with vertical sidewalls. The two-dimensional material is positioned within this 3D trench configuration, enabling improved channel control and device performance while managing manufacturing complexity through structured dimensional transition
2Manufacturing precision
If trench structure with multiple layers is formed, then control over channel region is improved, but fabrication process complexity increases
Solution Approach 1:
The trench structure is formed preliminarily before depositing the two-dimensional material layer. Source/drain electrode layers and dielectric layers are pre-positioned within the trench to establish precise geometric constraints that guide subsequent material deposition and ensure accurate channel region formation
Solution Approach 2:
Different regions of the device are assigned different material properties and structural characteristics. The trench sidewalls provide localized geometric control, while the two-dimensional material layer provides localized electrical channel properties. This local quality differentiation enables precise control over channel characteristics without requiring complex global fabrication processes
Data Source
AI summary
A semiconductor device includes a first dielectric layer on a substrate, a hard mask layer on the first dielectric layer, a trench in the hard mask layer and the first dielectric layer, a first source/drain electrode layer on a sidewall of the trench, a second dielectric layer on the first source/drain electrode layer in the trench, a second source/drain electrode layer on the second dielectric layer in the trench, a third dielectric layer on the second source/drain electrode layer in the trench, a 2D material layer overlying the hard mask layer, the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer, a gate dielectric layer on the 2D material layer, and a gate electrode on the gate dielectric layer.