Stacked FET Hybrid Contacts With BSPDN for Bottom S/D Access
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Solution Overview
Problem
Conventional contact architectures for stacked field effect transistors (FETs) face challenges in accessing the bottom source/drain epitaxial (S/D) regions due to blocking by top S/D epi, compromising scaling benefits and increasing costs with multiple wafer flips and gate printing.
Innovation Solution
A hybrid contact scheme integrating a backside power distribution network (BSPDN) with both frontside and backside contacts, utilizing buried power rails and deep trench contacts to establish electrical connections, allowing for single wafer flip and reduced misalignment, and enabling flexible device architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional contact architecture is used for stacked FETs, then all contacts are formed from the frontside of the wafer, but access to bottom source/drain epi is blocked by top source/drain epi
Solution Approach 1:
The patent introduces backside contacts that access the bottom source/drain epi from the opposite side of the wafer, adding a spatial dimension (frontside vs. backside) to the contact architecture. This resolves the blocking issue by approaching the target region from an unobstructed direction, allowing simultaneous access to both top and bottom S/D epi without interference.
Solution Approach 2:
The contact architecture is segmented into frontside contacts (accessing top S/D epi) and backside contacts (accessing bottom S/D epi). This division allows independent optimization of each contact path, with frontside contacts handling top device connections and backside contacts handling bottom device connections, eliminating the mutual blocking problem.
2Ease of operation
If bottom source/drain epi is extended to avoid blocking, then access issue is resolved, but scaling benefits are compromised
Solution Approach 1:
Instead of extending the bottom S/D epi laterally (compromising scaling), the patent accesses the bottom S/D epi from the backside of the wafer. This vertical/dimensional approach maintains compact lateral dimensions for scaling while providing unobstructed access to the bottom S/D region through the substrate.
3Ease of operation
If multiple wafer flips and gate printing are performed, then contact access is achieved, but costs increase
Solution Approach 1:
The backside contacts are formed in advance during the fabrication process, establishing access paths to the bottom S/D epi before final assembly. This preliminary action eliminates the need for subsequent wafer flips and re-printing operations, reducing both manufacturing complexity and cost.
Solution Approach 2:
By separating contact formation into frontside and backside operations that can be performed in parallel during fabrication, the patent eliminates sequential wafer flipping and re-printing steps, thereby reducing manufacturing cost and process complexity.
Data Source
AI summary
A semiconductor device including a hybrid contact scheme for stacked FET is disclosed with integration of a BSPDN. A double-sided (both frontside and backside of the wafer) contact scheme with buried power rail (BPR) and backside power distribution network (BSPDN) provides optimum contact and interconnect. The stacked FET could include, for example, FINFET over FINFET, FINFET over nanosheet, or nanosheet over nanosheet.